Lines Matching refs:qep
76 static inline u32 intel_qep_readl(struct intel_qep *qep, u32 offset)
78 return readl(qep->regs + offset);
81 static inline void intel_qep_writel(struct intel_qep *qep,
84 writel(value, qep->regs + offset);
87 static void intel_qep_init(struct intel_qep *qep)
91 reg = intel_qep_readl(qep, INTEL_QEPCON);
93 intel_qep_writel(qep, INTEL_QEPCON, reg);
94 qep->enabled = false;
99 reg = intel_qep_readl(qep, INTEL_QEPCON);
104 intel_qep_writel(qep, INTEL_QEPCON, reg);
105 intel_qep_writel(qep, INTEL_QEPINT_MASK, INTEL_QEPINT_MASK_ALL);
111 struct intel_qep *const qep = counter_priv(counter);
113 pm_runtime_get_sync(qep->dev);
114 *val = intel_qep_readl(qep, INTEL_QEPCOUNT);
115 pm_runtime_put(qep->dev);
178 struct intel_qep *qep = counter_priv(counter);
180 pm_runtime_get_sync(qep->dev);
181 *ceiling = intel_qep_readl(qep, INTEL_QEPMAX);
182 pm_runtime_put(qep->dev);
190 struct intel_qep *qep = counter_priv(counter);
197 mutex_lock(&qep->lock);
198 if (qep->enabled) {
203 pm_runtime_get_sync(qep->dev);
204 intel_qep_writel(qep, INTEL_QEPMAX, max);
205 pm_runtime_put(qep->dev);
208 mutex_unlock(&qep->lock);
215 struct intel_qep *qep = counter_priv(counter);
217 *enable = qep->enabled;
225 struct intel_qep *qep = counter_priv(counter);
229 mutex_lock(&qep->lock);
230 changed = val ^ qep->enabled;
234 pm_runtime_get_sync(qep->dev);
235 reg = intel_qep_readl(qep, INTEL_QEPCON);
239 pm_runtime_get_noresume(qep->dev);
242 pm_runtime_put_noidle(qep->dev);
245 intel_qep_writel(qep, INTEL_QEPCON, reg);
246 pm_runtime_put(qep->dev);
247 qep->enabled = val;
250 mutex_unlock(&qep->lock);
258 struct intel_qep *qep = counter_priv(counter);
261 pm_runtime_get_sync(qep->dev);
262 reg = intel_qep_readl(qep, INTEL_QEPCON);
264 pm_runtime_put(qep->dev);
267 reg = INTEL_QEPFLT_MAX_COUNT(intel_qep_readl(qep, INTEL_QEPFLT));
268 pm_runtime_put(qep->dev);
279 struct intel_qep *qep = counter_priv(counter);
303 mutex_lock(&qep->lock);
304 if (qep->enabled) {
309 pm_runtime_get_sync(qep->dev);
310 reg = intel_qep_readl(qep, INTEL_QEPCON);
315 intel_qep_writel(qep, INTEL_QEPFLT, length);
316 intel_qep_writel(qep, INTEL_QEPCON, reg);
317 pm_runtime_put(qep->dev);
320 mutex_unlock(&qep->lock);
328 struct intel_qep *qep = counter_priv(counter);
331 pm_runtime_get_sync(qep->dev);
332 reg = intel_qep_readl(qep, INTEL_QEPCON);
333 pm_runtime_put(qep->dev);
343 struct intel_qep *qep = counter_priv(counter);
347 mutex_lock(&qep->lock);
348 if (qep->enabled) {
353 pm_runtime_get_sync(qep->dev);
354 reg = intel_qep_readl(qep, INTEL_QEPCON);
360 intel_qep_writel(qep, INTEL_QEPCON, reg);
361 pm_runtime_put(qep->dev);
364 mutex_unlock(&qep->lock);
395 struct intel_qep *qep;
400 counter = devm_counter_alloc(dev, sizeof(*qep));
403 qep = counter_priv(counter);
419 qep->dev = dev;
420 qep->regs = regs;
421 mutex_init(&qep->lock);
423 intel_qep_init(qep);
424 pci_set_drvdata(pci, qep);
433 qep->enabled = false;
447 struct intel_qep *qep = pci_get_drvdata(pci);
451 if (!qep->enabled)
454 intel_qep_writel(qep, INTEL_QEPCON, 0);
460 struct intel_qep *qep = pci_get_drvdata(pdev);
462 qep->qepcon = intel_qep_readl(qep, INTEL_QEPCON);
463 qep->qepflt = intel_qep_readl(qep, INTEL_QEPFLT);
464 qep->qepmax = intel_qep_readl(qep, INTEL_QEPMAX);
472 struct intel_qep *qep = pci_get_drvdata(pdev);
479 intel_qep_writel(qep, INTEL_QEPCON, 0);
480 intel_qep_readl(qep, INTEL_QEPCON);
482 intel_qep_writel(qep, INTEL_QEPFLT, qep->qepflt);
483 intel_qep_writel(qep, INTEL_QEPMAX, qep->qepmax);
484 intel_qep_writel(qep, INTEL_QEPINT_MASK, INTEL_QEPINT_MASK_ALL);
487 intel_qep_writel(qep, INTEL_QEPCON, qep->qepcon & ~INTEL_QEPCON_EN);
488 intel_qep_readl(qep, INTEL_QEPCON);
491 intel_qep_writel(qep, INTEL_QEPCON, qep->qepcon);
510 .name = "intel-qep",