Lines Matching defs:channel
208 const size_t channel, const u8 val,
211 u8p_replace_bits(&buf[channel], val, field);
212 return regmap_write(map, QUAD8_CONTROL(channel), buf[channel]);
536 irq_enabled |= BIT(event_node->channel);
539 if (flg_pins == u8_get_bits(priv->ior[event_node->channel], FLG_PINS))
543 ret = quad8_control_register_update(priv->map, priv->ior, event_node->channel,
562 if (watch->channel > QUAD8_NUM_COUNTERS - 1)
571 if (watch->channel == event_node->channel &&
1197 unsigned long channel;
1209 for_each_set_bit(channel, &irq_status, QUAD8_NUM_COUNTERS) {
1210 flg_pins = u8_get_bits(priv->ior[channel], FLG_PINS);
1226 WARN_ONCE(true, "invalid interrupt trigger function %u configured for channel %lu\n",
1227 flg_pins, channel);
1231 counter_push_event(counter, event, channel);
1241 static int quad8_init_counter(struct quad8 *const priv, const size_t channel)
1245 ret = quad8_filter_clock_prescaler_set(priv, channel, 0);
1248 ret = quad8_preset_register_set(priv, channel, 0);
1251 ret = quad8_flag_register_reset(priv, channel);
1256 priv->cmr[channel] = SELECT_CMR | BINARY | u8_encode_bits(NORMAL_COUNT, COUNT_MODE) |
1258 ret = regmap_write(priv->map, QUAD8_CONTROL(channel), priv->cmr[channel]);
1263 priv->ior[channel] = SELECT_IOR | DISABLE_AB | u8_encode_bits(LOAD_CNTR, LOAD_PIN) |
1265 ret = regmap_write(priv->map, QUAD8_CONTROL(channel), priv->ior[channel]);
1270 priv->idr[channel] = SELECT_IDR | u8_encode_bits(DISABLE_INDEX_MODE, INDEX_MODE) |
1272 return regmap_write(priv->map, QUAD8_CONTROL(channel), priv->idr[channel]);