Lines Matching refs:timer
33 #include <clocksource/timer-ti-dm.h>
36 * timer errata flags
40 * timer counter register is never read. For more details please refer to
159 * dmtimer_read - read timer registers in posted and non-posted mode
160 * @timer: timer pointer over which read operation to perform
167 static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg)
175 if (wp && timer->posted)
176 while (readl_relaxed(timer->pend) & wp)
179 return readl_relaxed(timer->func_base + offset);
183 * dmtimer_write - write timer registers in posted and non-posted mode
184 * @timer: timer pointer over which write operation is to perform
192 static inline void dmtimer_write(struct dmtimer *timer, u32 reg, u32 val)
200 if (wp && timer->posted)
201 while (readl_relaxed(timer->pend) & wp)
204 writel_relaxed(val, timer->func_base + offset);
207 static inline void __omap_dm_timer_init_regs(struct dmtimer *timer)
212 tidr = readl_relaxed(timer->io_base);
214 timer->revision = 1;
215 timer->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
216 timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
217 timer->irq_dis = OMAP_TIMER_V1_INT_EN_OFFSET;
218 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
219 timer->func_base = timer->io_base;
221 timer->revision = 2;
222 timer->irq_stat = OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET;
223 timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET;
224 timer->irq_dis = OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFSET;
225 timer->pend = timer->io_base +
228 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
234 * @timer: pointer to timer instance handle
236 * Enables the write posted mode for the timer. When posted mode is enabled
237 * writes to certain timer registers are immediately acknowledged by the
240 * timer registers.
242 static inline void __omap_dm_timer_enable_posted(struct dmtimer *timer)
244 if (timer->posted)
247 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
248 timer->posted = OMAP_TIMER_NONPOSTED;
249 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0);
253 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED);
254 timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
255 timer->posted = OMAP_TIMER_POSTED;
258 static inline void __omap_dm_timer_stop(struct dmtimer *timer)
262 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
265 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
268 dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
271 * timer is stopped
273 udelay(3500000 / timer->fclk_rate + 1);
278 dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW);
281 static inline void __omap_dm_timer_int_enable(struct dmtimer *timer,
284 dmtimer_write(timer, timer->irq_ena, value);
285 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
289 __omap_dm_timer_read_counter(struct dmtimer *timer)
291 return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG);
294 static inline void __omap_dm_timer_write_status(struct dmtimer *timer,
297 dmtimer_write(timer, timer->irq_stat, value);
300 static void omap_timer_restore_context(struct dmtimer *timer)
302 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg);
304 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer);
305 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr);
306 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr);
307 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar);
308 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr);
309 dmtimer_write(timer, timer->irq_ena, timer->context.tier);
310 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr);
313 static void omap_timer_save_context(struct dmtimer *timer)
315 timer->context.ocp_cfg = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
317 timer->context.tclr = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
318 timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG);
319 timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG);
320 timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG);
321 timer->context.tier = dmtimer_read(timer, timer->irq_ena);
322 timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG);
328 struct dmtimer *timer;
330 timer = container_of(nb, struct dmtimer, nb);
334 if ((timer->capability & OMAP_TIMER_ALWON) ||
335 !atomic_read(&timer->enabled))
337 omap_timer_save_context(timer);
342 if ((timer->capability & OMAP_TIMER_ALWON) ||
343 !atomic_read(&timer->enabled))
345 omap_timer_restore_context(timer);
356 struct dmtimer *timer = container_of(nb, struct dmtimer, fclk_nb);
360 timer->fclk_rate = clk_data->new_rate;
367 static int omap_dm_timer_reset(struct dmtimer *timer)
371 if (timer->revision != 1)
374 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
377 l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET);
381 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
385 /* Configure timer for smart-idle mode */
386 l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
388 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l);
390 timer->posted = 0;
415 struct dmtimer *timer;
417 timer = to_dmtimer(cookie);
418 if (unlikely(!timer) || IS_ERR(timer->fclk))
435 pdata = timer->pdev->dev.platform_data;
442 if (timer->omap1 && pdata && pdata->set_timer_src)
443 return pdata->set_timer_src(timer->pdev, source);
447 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
451 parent = clk_get(&timer->pdev->dev, parent_name);
457 ret = clk_set_parent(timer->fclk, parent);
469 struct dmtimer *timer = to_dmtimer(cookie);
470 struct device *dev = &timer->pdev->dev;
475 dev_err(dev, "could not enable timer\n");
480 struct dmtimer *timer = to_dmtimer(cookie);
481 struct device *dev = &timer->pdev->dev;
486 static int omap_dm_timer_prepare(struct dmtimer *timer)
488 struct device *dev = &timer->pdev->dev;
495 if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
496 rc = omap_dm_timer_reset(timer);
503 __omap_dm_timer_enable_posted(timer);
516 struct dmtimer *timer = NULL, *t;
545 timer = t;
546 timer->reserved = 1;
553 * If timer is not NULL, we have already found
554 * one timer. But it was not an exact match
557 * timer found and see if this one is a better
560 if (timer)
561 timer->reserved = 0;
562 timer = t;
563 timer->reserved = 1;
572 timer = t;
573 timer->reserved = 1;
579 timer = t;
580 timer->reserved = 1;
587 if (timer && omap_dm_timer_prepare(timer)) {
588 timer->reserved = 0;
589 timer = NULL;
592 if (!timer)
593 pr_debug("%s: timer request failed!\n", __func__);
595 return timer;
600 struct dmtimer *timer;
602 timer = _omap_dm_timer_request(REQUEST_ANY, NULL);
603 if (!timer)
606 return &timer->cookie;
611 struct dmtimer *timer;
613 /* Requesting timer by ID is not supported when device tree is used */
620 timer = _omap_dm_timer_request(REQUEST_BY_ID, &id);
621 if (!timer)
624 return &timer->cookie;
628 * omap_dm_timer_request_by_node - Request a timer by device-tree node
629 * @np: Pointer to device-tree timer node
631 * Request a timer based upon a device node pointer. Returns pointer to
632 * timer handle on success and a NULL pointer on failure.
636 struct dmtimer *timer;
641 timer = _omap_dm_timer_request(REQUEST_BY_NODE, np);
642 if (!timer)
645 return &timer->cookie;
650 struct dmtimer *timer;
654 timer = to_dmtimer(cookie);
655 if (unlikely(!timer))
658 WARN_ON(!timer->reserved);
659 timer->reserved = 0;
661 dev = &timer->pdev->dev;
666 /* Clear timer configuration */
667 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
676 struct dmtimer *timer = to_dmtimer(cookie);
677 if (timer)
678 return timer->irq;
697 struct dmtimer *timer = NULL;
704 /* If any active timer is using ARMXOR return modified mask */
706 list_for_each_entry(timer, &omap_timer_list, node) {
709 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
727 struct dmtimer *timer = to_dmtimer(cookie);
729 if (timer && !IS_ERR(timer->fclk))
730 return timer->fclk;
745 struct dmtimer *timer;
750 timer = to_dmtimer(cookie);
751 if (unlikely(!timer))
754 dev = &timer->pdev->dev;
760 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
763 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
771 struct dmtimer *timer;
774 timer = to_dmtimer(cookie);
775 if (unlikely(!timer))
778 dev = &timer->pdev->dev;
780 __omap_dm_timer_stop(timer);
790 struct dmtimer *timer;
794 timer = to_dmtimer(cookie);
795 if (unlikely(!timer))
798 dev = &timer->pdev->dev;
803 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load);
813 struct dmtimer *timer;
818 timer = to_dmtimer(cookie);
819 if (unlikely(!timer))
822 dev = &timer->pdev->dev;
827 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
832 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match);
833 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
843 struct dmtimer *timer;
848 timer = to_dmtimer(cookie);
849 if (unlikely(!timer))
852 dev = &timer->pdev->dev;
857 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
867 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
876 struct dmtimer *timer;
881 timer = to_dmtimer(cookie);
882 if (unlikely(!timer))
885 dev = &timer->pdev->dev;
890 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
900 struct dmtimer *timer;
905 timer = to_dmtimer(cookie);
906 if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
909 dev = &timer->pdev->dev;
914 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
920 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
930 struct dmtimer *timer;
934 timer = to_dmtimer(cookie);
935 if (unlikely(!timer))
938 dev = &timer->pdev->dev;
943 __omap_dm_timer_int_enable(timer, value);
951 * omap_dm_timer_set_int_disable - disable timer interrupts
952 * @cookie: pointer to timer cookie
955 * Disables the specified timer interrupts for a timer.
959 struct dmtimer *timer;
964 timer = to_dmtimer(cookie);
965 if (unlikely(!timer))
968 dev = &timer->pdev->dev;
973 if (timer->revision == 1)
974 l = dmtimer_read(timer, timer->irq_ena) & ~mask;
976 dmtimer_write(timer, timer->irq_dis, l);
977 l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
978 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
987 struct dmtimer *timer;
990 timer = to_dmtimer(cookie);
991 if (unlikely(!timer || !atomic_read(&timer->enabled))) {
992 pr_err("%s: timer not available or enabled.\n", __func__);
996 l = dmtimer_read(timer, timer->irq_stat);
1003 struct dmtimer *timer;
1005 timer = to_dmtimer(cookie);
1006 if (unlikely(!timer || !atomic_read(&timer->enabled)))
1009 __omap_dm_timer_write_status(timer, value);
1016 struct dmtimer *timer;
1018 timer = to_dmtimer(cookie);
1019 if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1020 pr_err("%s: timer not iavailable or enabled.\n", __func__);
1024 return __omap_dm_timer_read_counter(timer);
1029 struct dmtimer *timer;
1031 timer = to_dmtimer(cookie);
1032 if (unlikely(!timer || !atomic_read(&timer->enabled))) {
1033 pr_err("%s: timer not available or enabled.\n", __func__);
1037 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value);
1040 timer->context.tcrr = value;
1046 struct dmtimer *timer = dev_get_drvdata(dev);
1048 atomic_set(&timer->enabled, 0);
1050 if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base)
1053 omap_timer_save_context(timer);
1060 struct dmtimer *timer = dev_get_drvdata(dev);
1062 if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base)
1063 omap_timer_restore_context(timer);
1065 atomic_set(&timer->enabled, 1);
1079 * @pdev: pointer to current timer platform device
1082 * timer devices.
1087 struct dmtimer *timer;
1103 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
1104 if (!timer)
1107 timer->irq = platform_get_irq(pdev, 0);
1108 if (timer->irq < 0)
1109 return timer->irq;
1111 timer->io_base = devm_platform_ioremap_resource(pdev, 0);
1112 if (IS_ERR(timer->io_base))
1113 return PTR_ERR(timer->io_base);
1115 platform_set_drvdata(pdev, timer);
1118 if (of_property_read_bool(dev->of_node, "ti,timer-alwon"))
1119 timer->capability |= OMAP_TIMER_ALWON;
1120 if (of_property_read_bool(dev->of_node, "ti,timer-dsp"))
1121 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
1122 if (of_property_read_bool(dev->of_node, "ti,timer-pwm"))
1123 timer->capability |= OMAP_TIMER_HAS_PWM;
1124 if (of_property_read_bool(dev->of_node, "ti,timer-secure"))
1125 timer->capability |= OMAP_TIMER_SECURE;
1127 timer->id = pdev->id;
1128 timer->capability = pdata->timer_capability;
1129 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
1132 timer->omap1 = timer->capability & OMAP_TIMER_NEEDS_RESET;
1135 if (!timer->omap1) {
1136 timer->fclk = devm_clk_get(dev, "fck");
1137 if (IS_ERR(timer->fclk))
1138 return PTR_ERR(timer->fclk);
1140 timer->fclk_nb.notifier_call = omap_timer_fclk_notifier;
1141 ret = devm_clk_notifier_register(dev, timer->fclk,
1142 &timer->fclk_nb);
1146 timer->fclk_rate = clk_get_rate(timer->fclk);
1148 timer->fclk = ERR_PTR(-ENODEV);
1151 if (!(timer->capability & OMAP_TIMER_ALWON)) {
1152 timer->nb.notifier_call = omap_timer_context_notifier;
1153 cpu_pm_register_notifier(&timer->nb);
1156 timer->errata = pdata->timer_errata;
1158 timer->pdev = pdev;
1162 if (!timer->reserved) {
1169 __omap_dm_timer_init_regs(timer);
1171 /* Clear timer configuration */
1172 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0);
1177 /* add the timer element to the list */
1179 list_add_tail(&timer->node, &omap_timer_list);
1192 * omap_dm_timer_remove - cleanup a registered timer device
1193 * @pdev: pointer to current timer platform device
1195 * Called by driver framework whenever a timer device is unregistered.
1196 * In addition to freeing platform resources it also deletes the timer
1201 struct dmtimer *timer;
1206 list_for_each_entry(timer, &omap_timer_list, node)
1207 if (!strcmp(dev_name(&timer->pdev->dev),
1209 if (!(timer->capability & OMAP_TIMER_ALWON))
1210 cpu_pm_unregister_notifier(&timer->nb);
1211 list_del(&timer->node);
1220 dev_err(&pdev->dev, "Unable to determine timer entry in list of drivers on remove\n");
1259 .compatible = "ti,omap2420-timer",
1262 .compatible = "ti,omap3430-timer",
1266 .compatible = "ti,omap4430-timer",
1270 .compatible = "ti,omap5430-timer",
1274 .compatible = "ti,am335x-timer",
1278 .compatible = "ti,am335x-timer-1ms",
1282 .compatible = "ti,dm816-timer",
1286 .compatible = "ti,am654-timer",