Lines Matching refs:base
38 void __iomem *base;
68 u32 tidr = readl_relaxed(t->base);
82 writel_relaxed(val, t->base + t->sysc);
90 writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc);
95 void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET;
100 writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
110 void __iomem *sysc = t->base + t->sysc;
371 t->base = of_iomap(np, 0);
372 if (!t->base)
416 pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base),
417 readl_relaxed(t->base + t->sysc));
422 iounmap(t->base);
439 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
450 void __iomem *pend = t->base + t->pend;
454 writel_relaxed(0xffffffff - cycles, t->base + t->counter);
458 writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
467 void __iomem *ctrl = t->base + t->ctrl;
479 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
488 void __iomem *pend = t->base + t->pend;
495 writel_relaxed(clkevt->period, t->base + t->load);
499 writel_relaxed(clkevt->period, t->base + t->counter);
504 t->base + t->ctrl);
529 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
530 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
576 writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl);
583 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
584 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
593 iounmap(t->base);
717 return (u64)readl_relaxed(t->base + t->counter);
732 clksrc->loadval = readl_relaxed(t->base + t->counter);
748 writel_relaxed(clksrc->loadval, t->base + t->counter);
750 t->base + t->ctrl);
783 writel_relaxed(0, t->base + t->counter);
785 t->base + t->ctrl);
792 dmtimer_sched_clock_counter = t->base + t->counter;