Lines Matching refs:ce
58 static void sun5i_clkevt_sync(struct sun5i_timer *ce)
60 u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1));
62 while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
66 static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer)
68 u32 val = readl(ce->base + TIMER_CTL_REG(timer));
69 writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer));
71 sun5i_clkevt_sync(ce);
74 static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 delay)
76 writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer));
79 static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool periodic)
81 u32 val = readl(ce->base + TIMER_CTL_REG(timer));
89 ce->base + TIMER_CTL_REG(timer));
94 struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
96 sun5i_clkevt_time_stop(ce, 0);
102 struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
104 sun5i_clkevt_time_stop(ce, 0);
105 sun5i_clkevt_time_start(ce, 0, false);
111 struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
113 sun5i_clkevt_time_stop(ce, 0);
114 sun5i_clkevt_time_setup(ce, 0, ce->ticks_per_jiffy);
115 sun5i_clkevt_time_start(ce, 0, true);
122 struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
124 sun5i_clkevt_time_stop(ce, 0);
125 sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
126 sun5i_clkevt_time_start(ce, 0, false);
133 struct sun5i_timer *ce = dev_id;
135 writel(0x1, ce->base + TIMER_IRQ_ST_REG);
136 ce->clkevt.event_handler(&ce->clkevt);
202 struct sun5i_timer *ce = platform_get_drvdata(pdev);
203 void __iomem *base = ce->base;
207 ce->clkevt.name = dev->of_node->name;
208 ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
209 ce->clkevt.set_next_event = sun5i_clkevt_next_event;
210 ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
211 ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;
212 ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;
213 ce->clkevt.tick_resume = sun5i_clkevt_shutdown;
214 ce->clkevt.rating = 340;
215 ce->clkevt.irq = irq;
216 ce->clkevt.cpumask = cpu_possible_mask;
222 clockevents_config_and_register(&ce->clkevt, rate,
227 "sun5i_timer0", ce);