Lines Matching refs:timer_of_base
56 #define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
57 #define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
143 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
144 writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
151 writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
160 writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
162 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
173 timer_of_base(to) + GPT_CTRL_REG(timer));
212 writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
222 timer_of_base(to) + GPT_CTRL_REG(timer));
225 timer_of_base(to) + GPT_CLK_REG(timer));
227 writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
230 timer_of_base(to) + GPT_CTRL_REG(timer));
238 writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
241 writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
243 val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
245 timer_of_base(to) + GPT_IRQ_EN_REG);
260 writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
267 writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
325 clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
328 gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);