Lines Matching defs:fttmr010
46 * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
77 * Interrupt status/mask register definitions for fttmr010/gemini/moxart
99 struct fttmr010 {
115 static struct fttmr010 *local_fttmr;
117 static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
119 return container_of(evt, struct fttmr010, clkevt);
145 struct fttmr010 *fttmr010 = to_fttmr010(evt);
149 fttmr010->timer_shutdown(evt);
151 if (fttmr010->is_aspeed) {
156 writel(cycles, fttmr010->base + TIMER1_LOAD);
159 cr = readl(fttmr010->base + TIMER1_COUNT);
160 writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
164 cr = readl(fttmr010->base + TIMER_CR);
165 cr |= fttmr010->t1_enable_val;
166 writel(cr, fttmr010->base + TIMER_CR);
173 struct fttmr010 *fttmr010 = to_fttmr010(evt);
176 writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR);
183 struct fttmr010 *fttmr010 = to_fttmr010(evt);
187 cr = readl(fttmr010->base + TIMER_CR);
188 cr &= ~fttmr010->t1_enable_val;
189 writel(cr, fttmr010->base + TIMER_CR);
196 struct fttmr010 *fttmr010 = to_fttmr010(evt);
200 fttmr010->timer_shutdown(evt);
203 writel(0, fttmr010->base + TIMER1_COUNT);
204 if (fttmr010->is_aspeed) {
205 writel(~0, fttmr010->base + TIMER1_LOAD);
207 writel(0, fttmr010->base + TIMER1_LOAD);
210 cr = readl(fttmr010->base + TIMER_INTR_MASK);
213 writel(cr, fttmr010->base + TIMER_INTR_MASK);
221 struct fttmr010 *fttmr010 = to_fttmr010(evt);
222 u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
226 fttmr010->timer_shutdown(evt);
229 if (fttmr010->is_aspeed) {
230 writel(period, fttmr010->base + TIMER1_LOAD);
233 writel(cr, fttmr010->base + TIMER1_COUNT);
234 writel(cr, fttmr010->base + TIMER1_LOAD);
237 cr = readl(fttmr010->base + TIMER_INTR_MASK);
240 writel(cr, fttmr010->base + TIMER_INTR_MASK);
244 cr = readl(fttmr010->base + TIMER_CR);
245 cr |= fttmr010->t1_enable_val;
246 writel(cr, fttmr010->base + TIMER_CR);
265 struct fttmr010 *fttmr010 = to_fttmr010(evt);
267 writel(0x1, fttmr010->base + TIMER_INTR_STATE);
276 struct fttmr010 *fttmr010;
298 fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
299 if (!fttmr010) {
303 fttmr010->tick_rate = clk_get_rate(clk);
305 fttmr010->base = of_iomap(np, 0);
306 if (!fttmr010->base) {
323 fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
325 fttmr010->is_aspeed = true;
327 fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
332 writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
333 writel(0, fttmr010->base + TIMER_INTR_STATE);
346 writel(val, fttmr010->base + TIMER_CR);
352 local_fttmr = fttmr010;
353 writel(0, fttmr010->base + TIMER2_COUNT);
354 writel(0, fttmr010->base + TIMER2_MATCH1);
355 writel(0, fttmr010->base + TIMER2_MATCH2);
357 if (fttmr010->is_aspeed) {
358 writel(~0, fttmr010->base + TIMER2_LOAD);
359 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
361 fttmr010->tick_rate,
364 fttmr010->tick_rate);
366 writel(0, fttmr010->base + TIMER2_LOAD);
367 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
369 fttmr010->tick_rate,
372 fttmr010->tick_rate);
378 writel(0, fttmr010->base + TIMER1_COUNT);
379 writel(0, fttmr010->base + TIMER1_LOAD);
380 writel(0, fttmr010->base + TIMER1_MATCH1);
381 writel(0, fttmr010->base + TIMER1_MATCH2);
384 fttmr010->timer_shutdown = ast2600_timer_shutdown;
387 &fttmr010->clkevt);
389 fttmr010->timer_shutdown = fttmr010_timer_shutdown;
392 &fttmr010->clkevt);
399 fttmr010->clkevt.name = "FTTMR010-TIMER1";
401 fttmr010->clkevt.rating = 300;
402 fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
404 fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
405 fttmr010->clkevt.set_state_shutdown = fttmr010->timer_shutdown;
406 fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
407 fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
408 fttmr010->clkevt.tick_resume = fttmr010->timer_shutdown;
409 fttmr010->clkevt.cpumask = cpumask_of(0);
410 fttmr010->clkevt.irq = irq;
411 clockevents_config_and_register(&fttmr010->clkevt,
412 fttmr010->tick_rate,
417 if (fttmr010->is_aspeed)
418 fttmr010->delay_timer.read_current_timer =
421 fttmr010->delay_timer.read_current_timer =
423 fttmr010->delay_timer.freq = fttmr010->tick_rate;
424 register_current_timer_delay(&fttmr010->delay_timer);
430 iounmap(fttmr010->base);
432 kfree(fttmr010);
454 TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);