Lines Matching defs:base_addr
69 * @base_addr: Base address of timer
75 void __iomem *base_addr;
116 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
118 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
120 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
128 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
145 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
161 return (u64)readl_relaxed(timer->base_addr +
199 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
201 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
221 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
223 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
266 readl_relaxed(ttccs->ttc.base_addr +
292 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
302 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
312 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
350 ttccs->ttc.base_addr = base;
362 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
364 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
366 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
433 ttcce->ttc.base_addr = base;
450 writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
452 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
453 writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);