Lines Matching refs:rate
25 * with a base rate of 5+ MHz, packaged as a clocksource (with
33 * the same rate as the clocksource
149 u32 rate;
208 writel((tcd->rate + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
273 clkevt.rate = clk_get_rate(t2_clk) / atmel_tcb_divisors[divisor_idx];
281 clkevt.rate = clk_get_rate(tc->slow_clk);
297 clockevents_config_and_register(&clkevt.clkevt, clkevt.rate, 1, BIT(bits) - 1);
381 u32 rate, divided_rate = 0;
435 rate = (u32) clk_get_rate(t0_clk);
443 tmp = rate / divisor;
444 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);