Lines Matching refs:cmt
91 struct sh_cmt_device *cmt;
244 return ch->cmt->info->read_control(ch->iostart, 0);
246 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
255 ch->cmt->info->write_control(ch->iostart, 0, value);
256 udelay(ch->cmt->reg_delay);
258 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
259 udelay(ch->cmt->reg_delay);
266 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
274 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
275 udelay(ch->cmt->reg_delay);
281 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
287 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2);
290 if (ch->cmt->info->model > SH_CMT_16BIT) {
298 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
305 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR);
308 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
309 udelay(ch->cmt->reg_delay);
318 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
326 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
340 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
349 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
356 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
359 ret = clk_enable(ch->cmt->clk);
361 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
370 if (ch->cmt->info->width == 16) {
374 u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ?
385 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
396 clk_disable(ch->cmt->clk);
411 clk_disable(ch->cmt->clk);
413 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
503 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
512 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
534 ch->cmt->info->clear_bits);
582 pm_runtime_get_sync(&ch->cmt->pdev->dev);
588 pm_runtime_get_sync(&ch->cmt->pdev->dev);
597 if (ch->cmt->num_channels == 1 &&
619 pm_runtime_put(&ch->cmt->pdev->dev);
629 pm_runtime_put(&ch->cmt->pdev->dev);
642 if (ch->cmt->num_channels == 1) {
695 dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
705 dev_pm_genpd_resume(&ch->cmt->pdev->dev);
721 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);
724 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
727 clocksource_register_hz(cs, ch->cmt->rate);
741 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
763 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
797 dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
798 clk_unprepare(ch->cmt->clk);
805 clk_prepare(ch->cmt->clk);
806 dev_pm_genpd_resume(&ch->cmt->pdev->dev);
816 irq = platform_get_irq(ch->cmt->pdev, ch->index);
822 dev_name(&ch->cmt->pdev->dev), ch);
824 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
843 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
849 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
862 ch->cmt->has_clockevent = true;
869 ch->cmt->has_clocksource = true;
878 bool clocksource, struct sh_cmt_device *cmt)
887 ch->cmt = cmt;
897 switch (cmt->info->model) {
899 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
903 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
907 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
912 value = ioread32(cmt->mapbase + CMCLKE);
914 iowrite32(value, cmt->mapbase + CMCLKE);
918 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
921 ch->max_match_value = (1 << cmt->info->width) - 1;
926 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
929 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
938 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
942 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
944 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
948 cmt->mapbase = ioremap(mem->start, resource_size(mem));
949 if (cmt->mapbase == NULL) {
950 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
958 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
959 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
967 .compatible = "renesas,cmt-48",
972 .compatible = "renesas,cmt-48-gen2",
1011 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
1017 cmt->pdev = pdev;
1018 raw_spin_lock_init(&cmt->lock);
1021 cmt->info = of_device_get_match_data(&pdev->dev);
1022 cmt->hw_channels = cmt->info->channels_mask;
1027 cmt->info = (const struct sh_cmt_info *)id->driver_data;
1028 cmt->hw_channels = cfg->channels_mask;
1030 dev_err(&cmt->pdev->dev, "missing platform data\n");
1035 cmt->clk = clk_get(&cmt->pdev->dev, "fck");
1036 if (IS_ERR(cmt->clk)) {
1037 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1038 return PTR_ERR(cmt->clk);
1041 ret = clk_prepare(cmt->clk);
1046 ret = clk_enable(cmt->clk);
1050 rate = clk_get_rate(cmt->clk);
1057 if (cmt->info->model >= SH_CMT_48BIT)
1058 cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate);
1059 cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8);
1062 ret = sh_cmt_map_memory(cmt);
1067 cmt->num_channels = hweight8(cmt->hw_channels);
1068 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1070 if (cmt->channels == NULL) {
1079 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1081 bool clocksource = i == 1 || cmt->num_channels == 1;
1084 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1085 clockevent, clocksource, cmt);
1092 clk_disable(cmt->clk);
1094 platform_set_drvdata(pdev, cmt);
1099 kfree(cmt->channels);
1100 iounmap(cmt->mapbase);
1102 clk_disable(cmt->clk);
1104 clk_unprepare(cmt->clk);
1106 clk_put(cmt->clk);
1112 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1120 if (cmt) {
1125 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1126 if (cmt == NULL)
1129 ret = sh_cmt_setup(cmt, pdev);
1131 kfree(cmt);
1139 if (cmt->has_clockevent || cmt->has_clocksource)