Lines Matching defs:channel
33 unsigned int channel;
83 regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));
97 regmap_write(tcu->map, TCU_REG_TDFRc(timer->channel), next);
98 regmap_write(tcu->map, TCU_REG_TCNTc(timer->channel), 0);
99 regmap_write(tcu->map, TCU_REG_TESR, BIT(timer->channel));
117 regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));
149 timer->clk = ingenic_tcu_get_clock(tcu->np, timer->channel);
169 timer_virq = irq_create_mapping(domain, timer->channel);
175 snprintf(timer->name, sizeof(timer->name), "TCU%u", timer->channel);
206 unsigned int channel = tcu->cs_channel;
211 tcu->cs_clk = ingenic_tcu_get_clock(np, channel);
225 /* Reset channel */
226 regmap_update_bits(tcu->map, TCU_REG_TCSRc(channel),
230 regmap_write(tcu->map, TCU_REG_TDFRc(channel), 0xffff);
231 regmap_write(tcu->map, TCU_REG_TCNTc(channel), 0);
233 /* Enable channel */
234 regmap_write(tcu->map, TCU_REG_TESR, BIT(channel));
296 * and channel 2 if target CPU is JZ4780/X2000 and SMP is selected.
306 pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__,
320 timer->channel = find_next_zero_bit(&tcu->pwm_channels_mask,
323 last_bit = timer->channel;