Lines Matching refs:rate
96 * @rate: Desired clock frequency
99 * Return: Frequency closest to @rate the hardware can generate
101 static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
107 /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */
108 if (rate > PS_PLL_VCO_MAX) {
109 div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);
110 rate = rate / div;
112 if (rate < PS_PLL_VCO_MIN) {
113 mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
114 rate = rate * mult;
117 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
120 rate = *prate * fbdiv;
123 return rate;
140 unsigned long rate, frac;
156 rate = parent_rate * fbdiv;
161 rate = rate + frac;
164 return rate;
168 * zynqmp_pll_set_rate() - Set rate of PLL
170 * @rate: Frequency of clock to be set
173 * Set PLL divider to set desired rate.
175 * Returns: rate which is set on success else error code
177 static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
187 rate_div = (rate * FRAC_DIV) / parent_rate;
194 rate = parent_rate * m;
206 return rate + frac;
209 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);