Lines Matching refs:clk_id
16 * @clk_id: PLL clock ID
21 u32 clk_id;
52 u32 clk_id = clk->clk_id;
57 ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload);
75 u32 clk_id = clk->clk_id;
85 ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode);
137 u32 clk_id = clk->clk_id;
145 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv);
158 zynqmp_pm_get_pll_frac_data(clk_id, ret_payload);
181 u32 clk_id = clk->clk_id;
197 ret = zynqmp_pm_clock_setdivider(clk_id, m);
204 zynqmp_pm_set_pll_frac_data(clk_id, f);
211 ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv);
229 u32 clk_id = clk->clk_id;
233 ret = zynqmp_pm_clock_getstate(clk_id, &state);
253 u32 clk_id = clk->clk_id;
265 ret = zynqmp_pm_clock_enable(clk_id);
281 u32 clk_id = clk->clk_id;
287 ret = zynqmp_pm_clock_disable(clk_id);
305 * @clk_id: Clock ID
312 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
335 pll->clk_id = clk_id;