Lines Matching refs:rate
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
50 unsigned long rate, u16 flags)
56 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
57 down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);
65 return (rate - up_rate) <= (down_rate - rate) ? up : down;
68 return DIV_ROUND_CLOSEST(parent_rate, rate);
73 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
75 * @parent_rate: rate of parent clock
114 * zynqmp_clk_divider_round_rate() - Round rate of divider clock
116 * @rate: rate of clock to be set
117 * @prate: rate of parent clock
122 unsigned long rate,
153 rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags);
155 if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate))
156 *prate = rate;
158 return rate;
162 * zynqmp_clk_divider_set_rate() - Set rate of divider clock
164 * @rate: rate of clock to be set
165 * @parent_rate: rate of parent clock
169 static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
179 value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
308 * To achieve best possible rate, maximum limit of divider is required