Lines Matching defs:clock
3 * Zynq UltraScale+ MPSoC clock controller
51 * @id: Parent clock ID
63 * @valid: Validity flag of clock
67 * @parent: Parent of clock
68 * @num_parents: Number of parents of clock
136 static struct zynqmp_clock *clock;
141 * zynqmp_is_valid_clock() - Check whether clock is valid or not
144 * Return: 1 if clock is valid, 0 if clock is invalid else error code
151 return clock[clk_id].valid;
155 * zynqmp_get_clock_name() - Get name of clock from Clock index
157 * @clk_name: Name of clock
167 strscpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
175 * zynqmp_get_clock_type() - Get type of clock
187 *type = clock[clk_id].type;
217 * zynqmp_pm_clock_get_name() - Get the name of clock for given id
218 * @clock_id: ID of the clock to be queried
219 * @response: Name of the clock with the given id
221 * This function is used to get name of clock specified by given
222 * clock ID.
246 * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
247 * @clock_id: ID of the clock to be queried
248 * @index: Node index of clock topology
251 * This function is used to get topology information for the clock
252 * specified by given clock ID.
301 * clock framework
302 * @name: Name of this clock
304 * @parents: Name of this clock's parents
308 * Return: clock hardware to the registered clock
343 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
346 * @response: Parents of the given clock
348 * This function is used to get 3 parents for the clock specified by
349 * given clock ID.
377 * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
381 * This function is used to get clock's attributes(e.g. valid, clock type, etc).
402 * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
437 * zynqmp_clock_get_topology() - Get topology of clock from firmware using
454 ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j,
468 * __zynqmp_clock_get_parents() - Get parents info of clock from firmware
521 ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j,
549 u32 total_parents = clock[clk_id].num_parents;
553 clk_nodes = clock[clk_id].node;
554 parents = clock[clk_id].parent;
560 ret = of_property_match_string(np, "clock-names",
578 * zynqmp_register_clk_topology() - Register clock topology
584 * Return: Returns either clock hardware or error+reason
596 nodes = clock[clk_id].node;
597 num_nodes = clock[clk_id].num_nodes;
598 clk_dev_id = clock[clk_id].clk_id;
602 * Clock name received from firmware is output clock name.
603 * Intermediate clock names are postfixed with type of clock.
648 /* get clock name, continue to next clock if name not found */
652 /* Check if clock is valid and output clock.
653 * Do not register invalid or external clock.
659 /* Get parents of clock*/
663 clock[i].clk_name);
676 clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));
684 * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
699 clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]);
700 /* skip query for Invalid clock */
705 clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ?
712 clock[i].clk_id = FIELD_PREP(CLK_ATTR_NODE_CLASS, class) |
717 zynqmp_pm_clock_get_name(clock[i].clk_id, &name);
727 strscpy(clock[i].clk_name, name.name, MAX_NAME_LEN);
730 /* Get topology of all clock */
736 ret = zynqmp_clock_get_topology(i, clock[i].node,
737 &clock[i].num_nodes);
741 ret = zynqmp_clock_get_parents(i, clock[i].parent,
742 &clock[i].num_parents);
749 * zynqmp_clk_setup() - Setup the clock framework and register clocks
767 clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL);
768 if (!clock) {