clk-xlnx-clock-wizard.c - OpenGrok cross reference for /kernel/linux/linux-6.6/drivers/clk/xilinx/clk-xlnx-clock-wizard.c

Lines Matching defs:base
89  * @base:		Memory base
100 	void __iomem *base;
113  * @base:	base address of register containing the divider
126 	void __iomem *base;
154 	void __iomem *div_addr = divider->base + divider->offset;
171 	void __iomem *div_addr = divider->base + divider->offset;
188 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
196 	       divider->base + WZRD_DR_INIT_REG_OFFSET);
198 	       divider->base + WZRD_DR_INIT_REG_OFFSET);
201 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
278 	writel(reg, divider->base + WZRD_CLK_CFG_REG(2));
282 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0));
283 	writel(divider->o, divider->base + WZRD_CLK_CFG_REG(2));
284 	writel(0, divider->base + WZRD_CLK_CFG_REG(3));
286 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
294 	       divider->base + WZRD_DR_INIT_REG_OFFSET);
297 	return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
324 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0));
327 	reg = readl(divider->base + WZRD_CLK_CFG_REG(2));
381 	void __iomem *div_addr = divider->base + divider->offset;
397 	void __iomem *div_addr = divider->base + divider->offset;
414 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
422 	       divider->base + WZRD_DR_INIT_REG_OFFSET);
424 	       divider->base + WZRD_DR_INIT_REG_OFFSET);
427 	return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
448 					  void __iomem *base, u16 offset,
471 	div->base = base;
491 					     void __iomem *base, u16 offset,
517 	div->base = base;
609 	clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0);
610 	if (IS_ERR(clk_wzrd->base))
611 		return PTR_ERR(clk_wzrd->base);
660 				clk_wzrd->base, WZRD_CLK_CFG_REG(3),
669 	reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0));
697 	ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0);
723 				clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),
732 				clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12),