Lines Matching defs:clock
182 "clock-output-names",
197 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
205 d->clocks[index].clk = clock;
212 dev_warn(d->dev, "clock %s con_id lookup may fail\n",
215 cl = clkdev_create(clock, con_id, NULL);
220 dev_warn(d->dev, "no con_id for clock %s\n", name);
226 d->outputs.clks[output_index] = clock;
242 struct clk *clock;
249 clock = clk_register_divider(d->dev, child_name, parent_name, 0,
252 if (IS_ERR(clock)) {
254 name, PTR_ERR(clock));
255 return PTR_ERR(clock);
258 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
271 struct clk *clock;
278 clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
280 if (IS_ERR(clock)) {
282 name, PTR_ERR(clock));
283 return PTR_ERR(clock);
286 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
300 struct clk *clock;
307 clock = clk_register_gate(d->dev, child_name, parent_name, 0,
310 if (IS_ERR(clock)) {
312 name, PTR_ERR(clock));
313 return PTR_ERR(clock);
316 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
329 struct clk *clock;
336 clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
338 if (IS_ERR(clock))
339 return PTR_ERR(clock);
341 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
380 * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
432 * Note that the DCO clock is never subject to bypass: if the PLL is off,
485 struct clk *clock;
516 /* Internal input clock divider N2 */
524 clock = devm_clk_register(d->dev, &d->dco.hw);
525 if (IS_ERR(clock))
526 return PTR_ERR(clock);
528 return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
581 struct clk *clock;
590 "clock-output-names",
620 clock = devm_clk_register(d->dev, &co->hw);
621 if (IS_ERR(clock)) {
623 name, PTR_ERR(clock));
624 return PTR_ERR(clock);
627 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
700 /* Output clock dcoclkldo is the DCO */
802 struct clk *clock;
812 clock = devm_clk_get(d->dev, d->parent_names[0]);
813 if (IS_ERR(clock)) {
815 return PTR_ERR(clock);
817 d->parent_clocks[TI_ADPLL_CLKINP] = clock;
819 clock = devm_clk_get(d->dev, d->parent_names[1]);
820 if (IS_ERR(clock)) {
821 dev_err(d->dev, "could not get clkinpulow clock\n");
822 return PTR_ERR(clock);
824 d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
827 clock = devm_clk_get(d->dev, d->parent_names[2]);
828 if (IS_ERR(clock)) {
829 dev_err(d->dev, "could not get clkinphif clock\n");
830 return PTR_ERR(clock);
832 d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
853 { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
854 { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
959 MODULE_ALIAS("platform:dm814-adpll-clock");