Lines Matching defs:clk_base
150 static void __iomem *clk_base;
819 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
822 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
828 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
831 clk_base + PLLM_OUT, 1, 0,
836 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
846 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,
851 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
861 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
874 clk_base + PLLE_AUX, 2, 1, 0, NULL);
897 clk_base + SUPER_CCLKG_DIVIDER, 0,
906 clk_base + SUPER_CCLKG_DIVIDER, 0,
915 clk_base + SUPER_CCLKG_DIVIDER, 0,
923 clk_base + CCLKG_BURST_POLICY,
932 clk_base + SUPER_CCLKLP_DIVIDER, 0,
941 clk_base + SUPER_CCLKLP_DIVIDER, 0,
950 clk_base + SUPER_CCLKLP_DIVIDER, 0,
958 clk_base + CCLKLP_BURST_POLICY,
968 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
1007 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1012 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1017 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1022 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);
1026 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1031 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1036 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1042 clk = tegra_clk_register_periph_data(clk_base, data);
1051 clk_base, data->offset);
1055 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1064 reg = readl(clk_base +
1075 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1082 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1089 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1090 readl(clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1097 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1099 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1108 cpu_rst_status = readl(clk_base +
1124 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1125 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
1128 readl(clk_base + CLK_RESET_CCLK_BURST);
1130 readl(clk_base + CLK_RESET_PLLX_BASE);
1132 readl(clk_base + CLK_RESET_PLLX_MISC);
1134 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1143 reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1154 misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);
1155 base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);
1161 clk_base + CLK_RESET_PLLX_MISC);
1163 clk_base + CLK_RESET_PLLX_BASE);
1176 clk_base + CLK_RESET_CCLK_DIVIDER);
1178 clk_base + CLK_RESET_CCLK_BURST);
1181 clk_base + CLK_RESET_SOURCE_CSITE);
1310 clk_base = of_iomap(np, 0);
1311 if (!clk_base) {
1329 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
1334 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1343 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
1369 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
1374 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1379 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
1387 clk_base + SCLK_BURST_POLICY,