Lines Matching defs:clk
8 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
20 #include "clk.h"
21 #include "clk-id.h"
184 static struct clk **clks;
667 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
668 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
669 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
670 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
671 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
815 struct clk *clk;
818 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
821 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
824 clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
827 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
830 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
833 clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
836 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
838 clks[TEGRA30_CLK_PLL_X] = clk;
841 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
843 clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
846 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,
848 clks[TEGRA30_CLK_PLL_U] = clk;
851 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
853 clks[TEGRA30_CLK_PLL_D] = clk;
856 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
858 clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
861 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
863 clks[TEGRA30_CLK_PLL_D2] = clk;
866 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
868 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
871 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
890 struct clk *clk;
896 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
899 clk_register_clkdev(clk, "pll_p_cclkg", NULL);
905 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
908 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
914 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
917 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
920 clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
925 clks[TEGRA30_CLK_CCLK_G] = clk;
931 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
934 clk_register_clkdev(clk, "pll_p_cclklp", NULL);
940 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
943 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
949 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
952 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
955 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
961 clks[TEGRA30_CLK_CCLK_LP] = clk;
964 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
966 clks[TEGRA30_CLK_TWD] = clk;
1003 struct clk *clk;
1007 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1009 clks[TEGRA30_CLK_DSIA] = clk;
1012 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1014 clks[TEGRA30_CLK_PCIE] = clk;
1017 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1019 clks[TEGRA30_CLK_AFI] = clk;
1022 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);
1024 clks[TEGRA30_CLK_EMC] = clk;
1026 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1028 clks[TEGRA30_CLK_MC] = clk;
1031 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1033 clks[TEGRA30_CLK_CML0] = clk;
1036 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1038 clks[TEGRA30_CLK_CML1] = clk;
1042 clk = tegra_clk_register_periph_data(clk_base, data);
1043 clks[data->clk_id] = clk;
1048 clk = tegra_clk_register_periph_nodiv(data->name,
1052 clks[data->clk_id] = clk;
1276 static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec,
1280 struct clk *clk;
1292 clk = of_clk_src_onecell_get(clkspec, data);
1293 if (IS_ERR(clk))
1294 return clk;
1296 hw = __clk_get_hw(clk);
1303 return clk;
1366 struct clk *clk;
1369 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
1371 clks[TEGRA30_CLK_PLL_C] = clk;
1374 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1376 clks[TEGRA30_CLK_PLL_E] = clk;
1379 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
1381 clks[TEGRA30_CLK_PLL_M] = clk;
1384 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1389 clks[TEGRA30_CLK_SCLK] = clk;