Lines Matching refs:params
739 struct tegra_clk_pll_params *params,
742 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
750 params->defaults_set = false;
759 static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
764 _pll_misc_chk_default(clk_base, params, 0, default_val,
768 _pll_misc_chk_default(clk_base, params, 1, default_val,
772 _pll_misc_chk_default(clk_base, params, 2, default_val,
776 _pll_misc_chk_default(clk_base, params, 3, default_val,
783 pllcx->params->defaults_set = true;
785 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
787 pllcx_check_defaults(pllcx->params);
788 if (!pllcx->params->defaults_set)
796 clk_base + pllcx->params->ext_misc_reg[0]);
798 clk_base + pllcx->params->ext_misc_reg[1]);
800 clk_base + pllcx->params->ext_misc_reg[2]);
802 clk_base + pllcx->params->ext_misc_reg[3]);
834 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
836 plla->params->defaults_set = true;
845 plla->params->defaults_set = false;
852 _pll_misc_chk_default(clk_base, plla->params, 0, val,
856 _pll_misc_chk_default(clk_base, plla->params, 2, val,
860 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
863 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
871 writel_relaxed(val, clk_base + plla->params->base_reg);
873 clk_base + plla->params->ext_misc_reg[0]);
875 clk_base + plla->params->ext_misc_reg[2]);
888 plld->params->defaults_set = true;
890 if (readl_relaxed(clk_base + plld->params->base_reg) &
898 _pll_misc_chk_default(clk_base, plld->params, 1,
905 _pll_misc_chk_default(clk_base, plld->params, 0, val,
908 if (!plld->params->defaults_set)
913 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
916 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
922 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
926 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
928 plld->params->ext_misc_reg[1]);
940 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
942 plldss->params->defaults_set = true;
952 plldss->params->defaults_set = false;
957 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
966 if (plldss->params->ssc_ctrl_en_mask) {
968 _pll_misc_chk_default(clk_base, plldss->params, 1,
971 _pll_misc_chk_default(clk_base, plldss->params, 2,
974 _pll_misc_chk_default(clk_base, plldss->params, 3,
976 } else if (plldss->params->ext_misc_reg[1]) {
978 _pll_misc_chk_default(clk_base, plldss->params, 1,
983 if (!plldss->params->defaults_set)
991 plldss->params->base_reg);
994 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
997 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
1006 writel_relaxed(val, clk_base + plldss->params->base_reg);
1009 if (!plldss->params->ext_misc_reg[1]) {
1011 plldss->params->ext_misc_reg[0]);
1017 plldss->params->ext_misc_reg[0]);
1020 clk_base + plldss->params->ext_misc_reg[1]);
1021 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
1022 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
1059 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
1061 pllre->params->defaults_set = true;
1074 pllre->params->defaults_set = false;
1080 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
1084 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1091 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
1094 if (!pllre->params->defaults_set)
1103 writel_relaxed(val, clk_base + pllre->params->base_reg);
1105 clk_base + pllre->params->ext_misc_reg[0]);
1149 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1153 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1158 _pll_misc_chk_default(clk_base, pll->params, 2,
1162 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1166 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1170 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1179 pllx->params->defaults_set = true;
1188 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1196 if (!pllx->params->defaults_set)
1199 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1202 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1205 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
1213 pllx->params->ext_misc_reg[0]);
1217 pllx->params->ext_misc_reg[1]);
1220 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1224 pllx->params->ext_misc_reg[3]);
1228 pllx->params->ext_misc_reg[4]);
1230 pllx->params->ext_misc_reg[5]);
1237 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1239 pllmb->params->defaults_set = true;
1249 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
1252 if (!pllmb->params->defaults_set)
1255 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1258 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
1266 clk_base + pllmb->params->ext_misc_reg[0]);
1285 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1291 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1298 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1300 pllp->params->defaults_set = true;
1309 if (!pllp->params->defaults_set)
1313 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1317 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
1325 clk_base + pllp->params->ext_misc_reg[0]);
1328 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1332 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1342 static void pllu_check_defaults(struct tegra_clk_pll_params *params,
1350 _pll_misc_chk_default(clk_base, params, 0, val,
1355 _pll_misc_chk_default(clk_base, params, 1, val,
1399 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1400 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1401 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1402 mask(p->params->div_nmp->divp_width))
1404 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1405 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1406 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1419 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
1435 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
1438 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1441 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1444 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1446 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1449 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
1452 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1454 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1455 writel_relaxed(base, clk_base + pllx->params->base_reg);
1459 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1465 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1483 struct tegra_clk_pll_params *params = pll->params;
1491 if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
1492 p = DIV_ROUND_UP(params->vco_min, rate);
1493 p = params->round_p_to_pdiv(p, &pdiv);
1495 p = rate >= params->vco_min ? 1 : -EINVAL;
1508 if (p_rate > params->vco_max)
1509 p_rate = params->vco_max;
1515 if (params->sdm_ctrl_reg) {
1518 if (rem || params->ssc_ctrl_reg) {
1555 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
1558 unsigned long vco_min = params->vco_min;
1560 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
1561 vco_min = min(vco_min, params->vco_min);
2910 pllu.params = &pll_u_vco_params;
2911 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2912 reg &= ~BIT(pllu.params->iddq_bit_idx);
2913 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);