Lines Matching defs:clk_base
298 static void __iomem *clk_base;
504 value = readl_relaxed(clk_base + PLLE_AUX);
520 value = readl_relaxed(clk_base + PLLE_MISC0);
525 writel_relaxed(value, clk_base + PLLE_MISC0);
527 value = readl_relaxed(clk_base + PLLE_AUX);
530 writel_relaxed(value, clk_base + PLLE_AUX);
532 fence_udelay(1, clk_base);
535 writel_relaxed(value, clk_base + PLLE_AUX);
537 fence_udelay(1, clk_base);
547 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
552 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
560 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
562 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
570 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
574 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
582 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
584 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
592 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
604 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
613 writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset);
619 writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL);
625 writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC);
633 val = readl_relaxed(clk_base + mbist->lvl2_offset);
634 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);
635 fence_udelay(1, clk_base);
636 writel_relaxed(val, clk_base + mbist->lvl2_offset);
637 fence_udelay(1, clk_base);
647 csi_src = readl_relaxed(clk_base + PLLD_BASE);
648 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
649 fence_udelay(1, clk_base);
651 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
652 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);
653 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
654 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);
655 fence_udelay(1, clk_base);
657 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
658 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
659 writel_relaxed(csi_src, clk_base + PLLD_BASE);
660 fence_udelay(1, clk_base);
669 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
670 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);
671 fence_udelay(1, clk_base);
679 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
680 fence_udelay(1, clk_base);
687 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
688 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);
689 fence_udelay(1, clk_base);
699 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
700 fence_udelay(1, clk_base);
709 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);
710 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
711 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);
713 clk_base + LVL2_CLK_GATE_OVRE);
714 fence_udelay(1, clk_base);
733 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);
734 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
735 fence_udelay(1, clk_base);
764 _pll_misc_chk_default(clk_base, params, 0, default_val,
768 _pll_misc_chk_default(clk_base, params, 1, default_val,
772 _pll_misc_chk_default(clk_base, params, 2, default_val,
776 _pll_misc_chk_default(clk_base, params, 3, default_val,
785 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
796 clk_base + pllcx->params->ext_misc_reg[0]);
798 clk_base + pllcx->params->ext_misc_reg[1]);
800 clk_base + pllcx->params->ext_misc_reg[2]);
802 clk_base + pllcx->params->ext_misc_reg[3]);
834 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
852 _pll_misc_chk_default(clk_base, plla->params, 0, val,
856 _pll_misc_chk_default(clk_base, plla->params, 2, val,
860 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
863 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
871 writel_relaxed(val, clk_base + plla->params->base_reg);
873 clk_base + plla->params->ext_misc_reg[0]);
875 clk_base + plla->params->ext_misc_reg[2]);
890 if (readl_relaxed(clk_base + plld->params->base_reg) &
898 _pll_misc_chk_default(clk_base, plld->params, 1,
905 _pll_misc_chk_default(clk_base, plld->params, 0, val,
913 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
916 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
922 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
926 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
927 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
940 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
957 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
968 _pll_misc_chk_default(clk_base, plldss->params, 1,
971 _pll_misc_chk_default(clk_base, plldss->params, 2,
974 _pll_misc_chk_default(clk_base, plldss->params, 3,
978 _pll_misc_chk_default(clk_base, plldss->params, 1,
990 writel_relaxed(val, clk_base +
994 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
997 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
1006 writel_relaxed(val, clk_base + plldss->params->base_reg);
1010 writel_relaxed(misc0_val, clk_base +
1016 writel_relaxed(misc0_val, clk_base +
1020 clk_base + plldss->params->ext_misc_reg[1]);
1021 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
1022 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
1059 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
1080 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
1084 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1091 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
1103 writel_relaxed(val, clk_base + pllre->params->base_reg);
1105 clk_base + pllre->params->ext_misc_reg[0]);
1149 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1153 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1158 _pll_misc_chk_default(clk_base, pll->params, 2,
1162 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1166 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1170 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1188 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1199 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1202 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1205 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
1212 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
1216 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
1220 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1223 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
1227 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
1229 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
1237 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1249 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
1255 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1258 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
1266 clk_base + pllmb->params->ext_misc_reg[0]);
1285 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1291 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1298 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1313 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1317 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
1325 clk_base + pllp->params->ext_misc_reg[0]);
1328 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1332 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1350 _pll_misc_chk_default(clk_base, params, 0, val,
1355 _pll_misc_chk_default(clk_base, params, 1, val,
1361 u32 val = readl_relaxed(clk_base + pllu->base_reg);
1376 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
1379 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
1381 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
1384 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
1392 clk_base + pllu->ext_misc_reg[0]);
1394 clk_base + pllu->ext_misc_reg[1]);
1421 val = readl_relaxed(clk_base + reg);
1438 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1441 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1444 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1446 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1452 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1455 writel_relaxed(base, clk_base + pllx->params->base_reg);
1459 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
2779 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2787 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2795 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2797 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2817 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2819 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2823 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2833 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2836 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2847 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2850 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2853 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2858 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2865 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2868 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2871 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2873 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2876 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2880 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2882 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2887 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2889 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2911 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2913 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
2914 fence_udelay(5, clk_base);
2916 reg = readl_relaxed(clk_base + PLLU_BASE);
2921 writel(reg, clk_base + PLLU_BASE);
2922 fence_udelay(1, clk_base);
2924 writel(reg, clk_base + PLLU_BASE);
2948 reg = readl_relaxed(clk_base + PLLU_BASE);
2958 reg = readl_relaxed(clk_base + PLLU_BASE);
2960 writel(reg, clk_base + PLLU_BASE);
2962 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2968 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2970 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2972 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2973 fence_udelay(1, clk_base);
2975 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2977 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2978 fence_udelay(1, clk_base);
2980 reg = readl_relaxed(clk_base + PLLU_BASE);
2982 writel_relaxed(reg, clk_base + PLLU_BASE);
2986 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
3041 clk_base + CLK_SOURCE_EMC,
3090 void __iomem *clk_base,
3101 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
3105 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
3109 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
3115 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
3120 clk_base, 0, 48,
3126 clk_base, 0, 82,
3132 CLK_SET_RATE_PARENT, clk_base + PLLD_BASE,
3139 ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
3144 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
3150 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
3156 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
3160 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
3165 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
3180 clk = tegra_clk_register_periph_data(clk_base, init);
3184 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
3187 clk = tegra210_clk_register_emc(np, clk_base);
3194 static void __init tegra210_pll_init(void __iomem *clk_base,
3200 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
3208 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3211 clk_base + PLLC_OUT, 1, 0,
3223 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
3229 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
3235 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
3241 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
3273 clk_base + PLLU_BASE, 16, 4, 0,
3280 clk_base + PLLU_OUTA, 0,
3284 clk_base + PLLU_OUTA, 1, 0,
3291 clk_base + PLLU_OUTA, 0,
3295 clk_base + PLLU_OUTA, 17, 16,
3302 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3309 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3316 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3322 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
3335 clk_base, pmc, 0,
3342 clk_base + PLLRE_BASE, 16, 5, 0,
3348 clk_base + PLLRE_OUT1, 0,
3352 clk_base + PLLRE_OUT1, 1, 0,
3358 clk_base, 0, &pll_e_params, NULL);
3363 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
3370 clk_base + PLLC4_BASE, 19, 4, 0,
3389 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3392 clk_base + PLLC4_OUT, 1, 0,
3398 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
3404 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
3429 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
3440 #define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
3442 writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
3457 spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0);
3458 misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
3459 clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
3472 tegra_clk_osc_resume(clk_base);
3478 writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0);
3479 writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
3480 writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM);
3492 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_L, clk_base + CLK_OUT_ENB_L);
3493 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_H, clk_base + CLK_OUT_ENB_H);
3494 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_U, clk_base + CLK_OUT_ENB_U);
3495 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_V, clk_base + CLK_OUT_ENB_V);
3496 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_W, clk_base + CLK_OUT_ENB_W);
3497 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_X, clk_base + CLK_OUT_ENB_X);
3498 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_Y, clk_base + CLK_OUT_ENB_Y);
3501 fence_udelay(2, clk_base);
3515 readl(clk_base + CLK_SOURCE_CSITE);
3516 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
3522 clk_base + CLK_SOURCE_CSITE);
3626 readl_relaxed(clk_base + RST_DFLL_DVCO);
3638 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3640 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3654 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3656 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3666 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);
3678 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3686 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3738 clk_base = of_iomap(np, 0);
3739 if (!clk_base) {
3777 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
3782 value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
3785 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
3791 tegra210_pll_init(clk_base, pmc_base);
3792 tegra210_periph_clk_init(np, clk_base, pmc_base);
3793 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
3798 value = readl(clk_base + PLLD_BASE);
3800 writel(value, clk_base + PLLD_BASE);
3804 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,