Lines Matching defs:cfg
275 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
276 (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))
1431 struct tegra_clk_pll_freq_table *cfg)
1440 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;
1454 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1463 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
1464 cfg->input_rate / cfg->m * cfg->n /
1465 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1479 struct tegra_clk_pll_freq_table *cfg,
1501 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
1502 cfg->p = p;
1505 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
1510 cf = input_rate / cfg->m;
1511 cfg->n = p_rate / cf;
1513 cfg->sdm_data = 0;
1514 cfg->output_rate = input_rate;
1516 unsigned long rem = p_rate - cf * cfg->n;
1523 cfg->sdm_data = sdin_din_to_data(s);
1525 cfg->output_rate *= sdin_get_n_eff(cfg);
1526 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
1528 cfg->output_rate *= cfg->n;
1529 cfg->output_rate /= p * cfg->m;
1532 cfg->input_rate = input_rate;
1540 * @cfg: struct tegra_clk_pll_freq_table * cfg
1548 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
1550 cfg->n = sdin_get_n_eff(cfg);
1551 cfg->m *= PLL_SDM_COEFF;