Lines Matching defs:pll_ref_div
576 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
581 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
585 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
589 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
593 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
608 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
611 switch (pll_ref_div) {
619 pr_err("Invalid pll ref divider %d\n", pll_ref_div);
859 unsigned int pll_ref_div;
869 pll_ref_div = tegra20_get_pll_ref_div();
871 CLK_SET_RATE_PARENT, 1, pll_ref_div);