Lines Matching defs:clk_base
132 static void __iomem *clk_base;
574 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
608 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
630 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
636 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
639 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
644 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
650 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
653 clk_base + PLLM_OUT, 1, 0,
658 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
663 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
668 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
678 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
684 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
687 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
692 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
711 clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK,
732 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
734 clk_base + AUDIO_SYNC_CLK, 4,
742 TEGRA_PERIPH_NO_RESET, clk_base,
792 clk_base, 0, 3, periph_clk_enb_refcnt);
796 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false);
800 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
805 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
811 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
817 0, clk_base + MISC_CLK_ENB, 22, 2,
823 0, clk_base + MISC_CLK_ENB, 20, 2,
829 clk_base, 0, 94, periph_clk_enb_refcnt);
834 clk_base, 0, 93, periph_clk_enb_refcnt);
839 clk = tegra_clk_register_periph_data(clk_base, data);
848 clk_base, data->offset);
852 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
881 reg = readl(clk_base +
892 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
899 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
907 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
909 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
911 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
918 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
920 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
928 cpu_rst_status = readl(clk_base +
938 readl(clk_base + CLK_SOURCE_CSITE);
939 writel(3<<30, clk_base + CLK_SOURCE_CSITE);
942 readl(clk_base + CCLK_BURST_POLICY);
944 readl(clk_base + PLLX_BASE);
946 readl(clk_base + PLLX_MISC);
948 readl(clk_base + SUPER_CCLK_DIVIDER);
957 reg = readl(clk_base + CCLK_BURST_POLICY);
968 misc = readl_relaxed(clk_base + PLLX_MISC);
969 base = readl_relaxed(clk_base + PLLX_BASE);
975 clk_base + PLLX_MISC);
977 clk_base + PLLX_BASE);
990 clk_base + SUPER_CCLK_DIVIDER);
992 clk_base + CCLK_BURST_POLICY);
995 clk_base + CLK_SOURCE_CSITE);
1121 clk_base = of_iomap(np, 0);
1122 if (!clk_base) {
1140 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
1149 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
1177 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);