Lines Matching defs:clk
7 #include <linux/clk-provider.h>
13 #include <linux/clk/tegra.h>
17 #include "clk.h"
18 #include "clk-id.h"
157 static struct clk **clks;
502 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
503 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
504 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
505 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
627 struct clk *clk;
630 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
632 clks[TEGRA20_CLK_PLL_C] = clk;
635 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
638 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
641 clks[TEGRA20_CLK_PLL_C_OUT1] = clk;
644 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
646 clks[TEGRA20_CLK_PLL_M] = clk;
649 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
652 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
655 clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
658 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
660 clks[TEGRA20_CLK_PLL_X] = clk;
663 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
665 clks[TEGRA20_CLK_PLL_U] = clk;
668 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
670 clks[TEGRA20_CLK_PLL_D] = clk;
673 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
675 clks[TEGRA20_CLK_PLL_D_OUT0] = clk;
678 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
680 clks[TEGRA20_CLK_PLL_A] = clk;
683 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
686 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
689 clks[TEGRA20_CLK_PLL_A_OUT0] = clk;
692 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
694 clks[TEGRA20_CLK_PLL_E] = clk;
706 struct clk *clk;
709 clk = tegra_clk_register_super_cclk("cclk", cclk_parents,
713 clks[TEGRA20_CLK_CCLK] = clk;
716 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
717 clks[TEGRA20_CLK_TWD] = clk;
726 struct clk *clk;
729 clk = clk_register_mux(NULL, "audio_mux", audio_parents,
733 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
736 clks[TEGRA20_CLK_AUDIO] = clk;
739 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
741 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
745 clks[TEGRA20_CLK_AUDIO_2X] = clk;
786 struct clk *clk;
790 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
793 clks[TEGRA20_CLK_AC97] = clk;
796 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false);
798 clks[TEGRA20_CLK_EMC] = clk;
800 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
802 clks[TEGRA20_CLK_MC] = clk;
805 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
807 clk_register_clkdev(clk, NULL, "dsi");
808 clks[TEGRA20_CLK_DSI] = clk;
811 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
813 clks[TEGRA20_CLK_PEX] = clk;
828 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0,
830 clks[TEGRA20_CLK_CDEV1] = clk;
833 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0,
835 clks[TEGRA20_CLK_CDEV2] = clk;
839 clk = tegra_clk_register_periph_data(clk_base, data);
840 clks[data->clk_id] = clk;
845 clk = tegra_clk_register_periph_nodiv(data->name,
849 clks[data->clk_id] = clk;
857 struct clk *clk;
864 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED,
866 clks[TEGRA20_CLK_CLK_M] = clk;
870 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
872 clks[TEGRA20_CLK_PLL_REF] = clk;
1072 static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
1077 struct clk *clk;
1089 clk = of_clk_src_onecell_get(clkspec, data);
1090 if (IS_ERR(clk))
1091 return clk;
1093 hw = __clk_get_hw(clk);
1097 * clock is created by the pinctrl driver. It is possible for clk user
1114 return clk;
1172 struct clk *clk;
1174 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1178 clks[TEGRA20_CLK_SCLK] = clk;