Lines Matching refs:val
58 u32 val, div;
60 val = readl_relaxed(emc->reg);
61 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
76 u32 val, div;
78 val = readl_relaxed(emc->reg);
79 val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK;
80 val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
82 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
85 val |= USE_PLLM_UD;
87 val &= ~USE_PLLM_UD;
90 val |= MC_EMC_SAME_FREQ;
92 val &= ~MC_EMC_SAME_FREQ;
94 writel_relaxed(val, emc->reg);
106 u32 val, div;
110 val = readl_relaxed(emc->reg);
111 val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
112 val |= div;
114 index = val >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
117 val |= USE_PLLM_UD;
119 val &= ~USE_PLLM_UD;
122 val |= MC_EMC_SAME_FREQ;
124 val &= ~MC_EMC_SAME_FREQ;
126 writel_relaxed(val, emc->reg);
139 u32 val, div;
143 val = readl_relaxed(emc->reg);
145 val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK;
146 val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
148 val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
149 val |= div;
152 val |= USE_PLLM_UD;
154 val &= ~USE_PLLM_UD;
157 val |= MC_EMC_SAME_FREQ;
159 val &= ~MC_EMC_SAME_FREQ;
161 writel_relaxed(val, emc->reg);