Lines Matching defs:clks
1022 static struct clk **clks;
1033 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1037 clks[TEGRA124_CLK_DPAUX] = clk;
1041 clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;
1046 clks[TEGRA124_CLK_DSIA] = clk;
1051 clks[TEGRA124_CLK_DSIB] = clk;
1055 clks[TEGRA124_CLK_MC] = clk;
1061 clks[TEGRA124_CLK_CML0] = clk;
1067 clks[TEGRA124_CLK_CML1] = clk;
1095 clks[TEGRA124_CLK_PLL_C] = clk;
1105 clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
1111 clks[TEGRA124_CLK_PLL_C_UD] = clk;
1117 clks[TEGRA124_CLK_PLL_C2] = clk;
1123 clks[TEGRA124_CLK_PLL_C3] = clk;
1129 clks[TEGRA124_CLK_PLL_M] = clk;
1139 clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
1145 clks[TEGRA124_CLK_PLL_M_UD] = clk;
1151 clks[TEGRA124_CLK_PLL_U] = clk;
1158 clks[TEGRA124_CLK_PLL_U_480M] = clk;
1164 clks[TEGRA124_CLK_PLL_U_60M] = clk;
1170 clks[TEGRA124_CLK_PLL_U_48M] = clk;
1176 clks[TEGRA124_CLK_PLL_U_12M] = clk;
1182 clks[TEGRA124_CLK_PLL_D] = clk;
1188 clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
1194 clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
1200 clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
1206 clks[TEGRA124_CLK_PLL_E] = clk;
1212 clks[TEGRA124_CLK_PLL_C4] = clk;
1218 clks[TEGRA124_CLK_PLL_DP] = clk;
1224 clks[TEGRA124_CLK_PLL_D2] = clk;
1230 clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
1368 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1369 tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
1444 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1445 tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
1482 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
1484 if (!clks)
1543 clks[TEGRA124_CLK_EMC] = tegra124_clk_register_emc(clk_base, np,