Lines Matching refs:tegra
3 * drivers/clk/tegra/clk-emc.c
14 #include <linux/clk/tegra.h>
25 #include <soc/tegra/fuse.h>
94 struct tegra_clk_emc *tegra;
97 tegra = container_of(hw, struct tegra_clk_emc, hw);
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
118 struct tegra_clk_emc *tegra;
123 tegra = container_of(hw, struct tegra_clk_emc, hw);
125 for (k = 0; k < tegra->num_timings; k++) {
126 if (tegra->timings[k].ram_code == ram_code)
130 for (t = k; t < tegra->num_timings; t++) {
131 if (tegra->timings[t].ram_code != ram_code)
136 timing = tegra->timings + i;
143 req->rate = tegra->timings[i - 1].rate;
165 struct tegra_clk_emc *tegra;
168 tegra = container_of(hw, struct tegra_clk_emc, hw);
170 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
176 static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
180 if (tegra->emc)
181 return tegra->emc;
183 if (!tegra->prepare_timing_change || !tegra->complete_timing_change)
186 if (!tegra->emc_node)
189 pdev = of_find_device_by_node(tegra->emc_node);
196 of_node_put(tegra->emc_node);
197 tegra->emc_node = NULL;
199 tegra->emc = platform_get_drvdata(pdev);
200 if (!tegra->emc) {
206 return tegra->emc;
209 static int emc_set_timing(struct tegra_clk_emc *tegra,
216 struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
224 if (emc_get_parent(&tegra->hw) == timing->parent_index &&
233 tegra->changing_timing = true;
252 err = tegra->prepare_timing_change(emc, timing->rate);
258 spin_lock_irqsave(tegra->lock, flags);
260 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
268 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
270 spin_unlock_irqrestore(tegra->lock, flags);
272 tegra->complete_timing_change(emc, timing->rate);
274 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
275 clk_disable_unprepare(tegra->prev_parent);
277 tegra->prev_parent = timing->parent;
278 tegra->changing_timing = false;
289 static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
296 for (i = timing_index+1; i < tegra->num_timings; i++) {
297 timing = tegra->timings + i;
303 tegra->timings[timing_index].parent_index])
308 timing = tegra->timings + i;
314 tegra->timings[timing_index].parent_index])
324 struct tegra_clk_emc *tegra;
329 tegra = container_of(hw, struct tegra_clk_emc, hw);
339 if (tegra->changing_timing)
342 for (i = 0; i < tegra->num_timings; i++) {
343 if (tegra->timings[i].rate == rate &&
344 tegra->timings[i].ram_code == ram_code) {
345 timing = tegra->timings + i;
365 backup_timing = get_backup_timing(tegra, i);
374 err = emc_set_timing(tegra, backup_timing);
381 return emc_set_timing(tegra, timing);
386 static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
442 static int load_timings_from_dt(struct tegra_clk_emc *tegra,
452 size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);
454 tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);
455 if (!tegra->timings)
458 timings_ptr = tegra->timings + tegra->num_timings;
459 tegra->num_timings += child_count;
464 err = load_one_timing_from_dt(tegra, timing, child);
467 kfree(tegra->timings);
490 struct tegra_clk_emc *tegra;
497 tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
498 if (!tegra)
501 tegra->clk_regs = base;
502 tegra->lock = lock;
504 tegra->num_timings = 0;
516 err = load_timings_from_dt(tegra, node, node_ram_code);
519 kfree(tegra);
524 if (tegra->num_timings == 0)
527 tegra->emc_node = of_parse_phandle(np,
529 if (!tegra->emc_node)
538 tegra->hw.init = &init;
540 clk = clk_register(NULL, &tegra->hw);
544 tegra->prev_parent = clk_hw_get_parent_by_index(
545 &tegra->hw, emc_get_parent(&tegra->hw))->clk;
546 tegra->changing_timing = false;
549 clk_register_clkdev(clk, "emc", "tegra-clk-debug");
558 struct tegra_clk_emc *tegra;
563 tegra = container_of(hw, struct tegra_clk_emc, hw);
565 tegra->prepare_timing_change = prep_cb;
566 tegra->complete_timing_change = complete_cb;
573 struct tegra_clk_emc *tegra = container_of(hw, struct tegra_clk_emc, hw);
575 return tegra->prepare_timing_change && tegra->complete_timing_change;