Lines Matching defs:clk_base
130 static void __iomem *clk_base;
890 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
899 static void __init tegra114_pll_init(void __iomem *clk_base,
905 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
911 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
914 clk_base + PLLC_OUT, 1, 0,
919 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
924 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
929 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
935 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
938 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
947 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
953 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
973 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
983 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
993 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
998 clk_base + PLLRE_BASE, 16, 4, 0,
1004 clk_base, 0, &pll_e_params, NULL);
1014 static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1030 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1037 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1040 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1044 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1052 clk_base + CLK_SOURCE_EMC,
1055 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1059 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
1066 clk = tegra_clk_register_periph_data(clk_base, data);
1070 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1080 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1095 readl(clk_base + CLK_SOURCE_CSITE);
1096 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1099 readl(clk_base + CCLKG_BURST_POLICY);
1101 readl(clk_base + CCLKG_BURST_POLICY + 4);
1107 clk_base + CLK_SOURCE_CSITE);
1110 clk_base + CCLKG_BURST_POLICY);
1112 clk_base + CCLKG_BURST_POLICY + 4);
1188 readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
1206 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1233 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1255 writel_relaxed(r, clk_base + CPU_FINETRIM_R);
1264 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
1279 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1281 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1296 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1298 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1307 clk_base = of_iomap(np, 0);
1308 if (!clk_base) {
1328 clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
1333 if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
1338 tegra114_fixed_clk_init(clk_base);
1339 tegra114_pll_init(clk_base, pmc_base);
1340 tegra114_periph_clk_init(clk_base, pmc_base);
1341 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
1344 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,