Lines Matching refs:pll_params
1202 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1205 u16 mdiv = parent_rate / pll_params->cf_min;
1207 if (pll_params->flags & TEGRA_MDIV_NEW)
1208 return (!pll_params->mdiv_default ? mdiv :
1209 min(mdiv, pll_params->mdiv_default));
1211 if (pll_params->mdiv_default)
1212 return pll_params->mdiv_default;
1214 if (parent_rate > pll_params->cf_max)
1267 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1296 val = step_a << pll_params->stepa_shift;
1297 val |= step_b << pll_params->stepb_shift;
1298 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1870 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1882 pll->params = pll_params;
1885 if (!pll_params->div_nmp)
1886 pll_params->div_nmp = &default_nmp;
1922 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1928 pll_params->flags |= TEGRA_PLL_BYPASS;
1930 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1953 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1959 pll_params->flags |= TEGRA_PLL_BYPASS;
1961 if (!pll_params->div_nmp)
1962 pll_params->div_nmp = &pll_e_nmp;
1964 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1978 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1983 pll_params->flags |= TEGRA_PLLU;
1985 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2045 struct tegra_clk_pll_params *pll_params,
2060 if (!pll_params->pdiv_tohw)
2065 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2067 if (pll_params->adjust_vco)
2068 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2075 if (!pll_params->set_defaults) {
2078 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2082 val = readl_relaxed(clk_base + pll_params->base_reg);
2083 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2086 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2088 val_iddq |= BIT(pll_params->iddq_bit_idx);
2090 clk_base + pll_params->iddq_reg);
2094 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2109 struct tegra_clk_pll_params *pll_params,
2116 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2118 if (pll_params->adjust_vco)
2119 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2122 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2130 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2131 BIT(pll_params->iddq_bit_idx));
2135 m = _pll_fixed_mdiv(pll_params, parent_rate);
2137 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2158 struct tegra_clk_pll_params *pll_params,
2165 if (!pll_params->pdiv_tohw)
2177 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2179 if (pll_params->adjust_vco)
2180 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2183 pll_params->flags |= TEGRA_PLL_BYPASS;
2184 pll_params->flags |= TEGRA_PLLM;
2185 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2200 struct tegra_clk_pll_params *pll_params,
2204 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2221 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2223 pll_params->flags |= TEGRA_PLL_BYPASS;
2224 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2237 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2238 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2257 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2258 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2259 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2274 struct tegra_clk_pll_params *pll_params,
2280 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2297 struct tegra_clk_pll_params *pll_params,
2303 pll_params->flags |= TEGRA_PLLU;
2305 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2331 struct tegra_clk_pll_params *pll_params,
2341 if (!pll_params->div_nmp)
2351 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2361 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2365 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2366 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2368 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2375 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2380 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2381 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2382 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2385 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2387 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2393 val_iddq |= BIT(pll_params->iddq_bit_idx);
2394 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2414 struct tegra_clk_pll_params *pll_params,
2420 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2422 if (pll_params->adjust_vco)
2423 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2426 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2577 struct tegra_clk_pll_params *pll_params,
2583 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2600 struct tegra_clk_pll_params *pll_params,
2604 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2620 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2622 if (pll_params->adjust_vco)
2623 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2626 pll_params->flags |= TEGRA_PLL_BYPASS;
2627 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2642 struct tegra_clk_pll_params *pll_params,
2650 if (!pll_params->div_nmp)
2660 val = readl_relaxed(clk_base + pll_params->base_reg);
2668 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2670 if (pll_params->adjust_vco)
2671 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2674 pll_params->flags |= TEGRA_PLL_BYPASS;
2675 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2691 struct tegra_clk_pll_params *pll_params,
2698 if (!pll_params->pdiv_tohw)
2710 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2712 if (pll_params->adjust_vco)
2713 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2716 pll_params->flags |= TEGRA_PLL_BYPASS;
2717 pll_params->flags |= TEGRA_PLLMB;
2718 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);