Lines Matching refs:pll
276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
286 val = pll_readl_misc(pll);
287 val |= BIT(pll->params->lock_enable_bit_idx);
288 pll_writel_misc(val, pll);
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
298 udelay(pll->params->lock_delay);
302 lock_addr = pll->clk_base;
303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
304 lock_addr += pll->params->misc_reg;
306 lock_addr += pll->params->base_reg;
308 lock_mask = pll->params->lock_mask;
310 for (i = 0; i < pll->params->lock_delay; i++) {
319 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
320 clk_hw_get_name(&pll->hw));
325 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
327 return clk_pll_wait_for_lock(pll);
330 static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll)
332 u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
340 struct tegra_clk_pll *pll = to_clk_pll(hw);
348 if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
351 val = pll_readl_base(pll);
358 struct tegra_clk_pll *pll = to_clk_pll(hw);
361 if (pll->params->iddq_reg) {
362 val = pll_readl(pll->params->iddq_reg, pll);
363 val &= ~BIT(pll->params->iddq_bit_idx);
364 pll_writel(val, pll->params->iddq_reg, pll);
368 if (pll->params->reset_reg) {
369 val = pll_readl(pll->params->reset_reg, pll);
370 val &= ~BIT(pll->params->reset_bit_idx);
371 pll_writel(val, pll->params->reset_reg, pll);
374 clk_pll_enable_lock(pll);
376 val = pll_readl_base(pll);
377 if (pll->params->flags & TEGRA_PLL_BYPASS)
380 pll_writel_base(val, pll);
382 if (pll->params->flags & TEGRA_PLLM) {
383 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
385 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
391 struct tegra_clk_pll *pll = to_clk_pll(hw);
394 val = pll_readl_base(pll);
395 if (pll->params->flags & TEGRA_PLL_BYPASS)
398 pll_writel_base(val, pll);
400 if (pll->params->flags & TEGRA_PLLM) {
401 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
403 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
406 if (pll->params->reset_reg) {
407 val = pll_readl(pll->params->reset_reg, pll);
408 val |= BIT(pll->params->reset_bit_idx);
409 pll_writel(val, pll->params->reset_reg, pll);
412 if (pll->params->iddq_reg) {
413 val = pll_readl(pll->params->iddq_reg, pll);
414 val |= BIT(pll->params->iddq_bit_idx);
415 pll_writel(val, pll->params->iddq_reg, pll);
420 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
425 val |= pll->params->ssc_ctrl_en_mask;
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
430 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
432 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
435 val &= ~pll->params->ssc_ctrl_en_mask;
436 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
442 struct tegra_clk_pll *pll = to_clk_pll(hw);
449 if (pll->lock)
450 spin_lock_irqsave(pll->lock, flags);
454 ret = clk_pll_wait_for_lock(pll);
456 pll_clk_start_ss(pll);
458 if (pll->lock)
459 spin_unlock_irqrestore(pll->lock, flags);
466 struct tegra_clk_pll *pll = to_clk_pll(hw);
469 if (pll->lock)
470 spin_lock_irqsave(pll->lock, flags);
472 pll_clk_stop_ss(pll);
476 if (pll->lock)
477 spin_unlock_irqrestore(pll->lock, flags);
482 struct tegra_clk_pll *pll = to_clk_pll(hw);
483 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
496 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
498 return _p_div_to_hw(&pll->hw, p_div);
503 struct tegra_clk_pll *pll = to_clk_pll(hw);
504 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
522 struct tegra_clk_pll *pll = to_clk_pll(hw);
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
534 if (pll->params->pdiv_tohw) {
556 struct tegra_clk_pll *pll = to_clk_pll(hw);
598 if (cfg->m == 0 || cfg->m > divm_max(pll) ||
599 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
600 cfg->output_rate > pll->params->vco_max) {
607 if (pll->params->pdiv_tohw) {
630 struct tegra_clk_pll *pll = to_clk_pll(hw);
634 if (!pll->params->sdm_din_reg)
638 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
639 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
640 pll_writel_sdm_din(val, pll);
643 val = pll_readl_sdm_ctrl(pll);
644 enabled = (val & sdm_en_mask(pll));
647 val &= ~pll->params->sdm_ctrl_en_mask;
650 val |= pll->params->sdm_ctrl_en_mask;
652 pll_writel_sdm_ctrl(val, pll);
655 static void _update_pll_mnp(struct tegra_clk_pll *pll,
659 struct tegra_clk_pll_params *params = pll->params;
663 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
665 val = pll_override_readl(params->pmc_divp_reg, pll);
666 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
668 pll_override_writel(val, params->pmc_divp_reg, pll);
670 val = pll_override_readl(params->pmc_divnm_reg, pll);
671 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
672 (divn_mask(pll) << div_nmp->override_divn_shift));
675 pll_override_writel(val, params->pmc_divnm_reg, pll);
677 val = pll_readl_base(pll);
679 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
680 divp_mask_shifted(pll));
682 val |= (cfg->m << divm_shift(pll)) |
683 (cfg->n << divn_shift(pll)) |
684 (cfg->p << divp_shift(pll));
686 pll_writel_base(val, pll);
688 clk_pll_set_sdm_data(&pll->hw, cfg);
692 static void _get_pll_mnp(struct tegra_clk_pll *pll,
696 struct tegra_clk_pll_params *params = pll->params;
702 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
704 val = pll_override_readl(params->pmc_divp_reg, pll);
705 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
707 val = pll_override_readl(params->pmc_divnm_reg, pll);
708 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
709 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
711 val = pll_readl_base(pll);
713 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
714 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
715 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
717 if (pll->params->sdm_din_reg) {
718 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
719 val = pll_readl_sdm_din(pll);
720 val &= sdm_din_mask(pll);
727 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
733 val = pll_readl_misc(pll);
738 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
742 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
744 if (rate >= (pll->params->vco_max >> 1))
748 pll_writel_misc(val, pll);
754 struct tegra_clk_pll *pll = to_clk_pll(hw);
760 if (state && pll->params->pre_rate_change) {
761 ret = pll->params->pre_rate_change();
766 _get_pll_mnp(pll, &old_cfg);
768 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
770 ret = pll->params->dyn_ramp(pll, cfg);
776 pll_clk_stop_ss(pll);
780 if (!pll->params->defaults_set && pll->params->set_defaults)
781 pll->params->set_defaults(pll);
783 _update_pll_mnp(pll, cfg);
785 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
786 _update_pll_cpcon(pll, cfg, rate);
790 ret = clk_pll_wait_for_lock(pll);
791 pll_clk_start_ss(pll);
795 if (state && pll->params->post_rate_change)
796 pll->params->post_rate_change();
804 struct tegra_clk_pll *pll = to_clk_pll(hw);
809 if (pll->params->flags & TEGRA_PLL_FIXED) {
810 if (rate != pll->params->fixed_rate) {
813 pll->params->fixed_rate, rate);
820 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
826 if (pll->lock)
827 spin_lock_irqsave(pll->lock, flags);
829 _get_pll_mnp(pll, &old_cfg);
830 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
837 if (pll->lock)
838 spin_unlock_irqrestore(pll->lock, flags);
846 struct tegra_clk_pll *pll = to_clk_pll(hw);
849 if (pll->params->flags & TEGRA_PLL_FIXED) {
851 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
853 return pll->params->fixed_rate;
857 pll->params->calc_rate(hw, &cfg, rate, *prate))
866 struct tegra_clk_pll *pll = to_clk_pll(hw);
872 val = pll_readl_base(pll);
874 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
877 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
878 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
881 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
887 return pll->params->fixed_rate;
890 _get_pll_mnp(pll, &cfg);
892 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
903 if (pll->params->set_gain)
904 pll->params->set_gain(&cfg);
914 static int clk_plle_training(struct tegra_clk_pll *pll)
919 if (!pll->pmc)
926 val = readl(pll->pmc + PMC_SATA_PWRGT);
928 writel(val, pll->pmc + PMC_SATA_PWRGT);
930 val = readl(pll->pmc + PMC_SATA_PWRGT);
932 writel(val, pll->pmc + PMC_SATA_PWRGT);
934 val = readl(pll->pmc + PMC_SATA_PWRGT);
936 writel(val, pll->pmc + PMC_SATA_PWRGT);
938 val = pll_readl_misc(pll);
942 val = pll_readl_misc(pll);
957 struct tegra_clk_pll *pll = to_clk_pll(hw);
968 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
973 val = pll_readl_misc(pll);
975 pll_writel_misc(val, pll);
977 val = pll_readl_misc(pll);
979 err = clk_plle_training(pll);
984 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
986 val = pll_readl_base(pll);
987 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
988 divm_mask_shifted(pll));
990 val |= sel.m << divm_shift(pll);
991 val |= sel.n << divn_shift(pll);
992 val |= sel.p << divp_shift(pll);
994 pll_writel_base(val, pll);
997 val = pll_readl_misc(pll);
1000 pll_writel_misc(val, pll);
1002 val = readl(pll->clk_base + PLLE_SS_CTRL);
1005 writel(val, pll->clk_base + PLLE_SS_CTRL);
1007 val = pll_readl_base(pll);
1009 pll_writel_base(val, pll);
1011 clk_pll_wait_for_lock(pll);
1019 struct tegra_clk_pll *pll = to_clk_pll(hw);
1020 u32 val = pll_readl_base(pll);
1024 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1025 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1026 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1036 struct tegra_clk_pll *pll = to_clk_pll(hw);
1044 if (pll->params->set_defaults)
1045 pll->params->set_defaults(pll);
1118 struct tegra_clk_pll *pll = to_clk_pll(hw);
1134 if (pll->lock)
1135 spin_lock_irqsave(pll->lock, flags);
1140 ret = clk_pll_wait_for_lock(pll);
1158 value = pll_readl_base(pll);
1160 pll_writel_base(value, pll);
1162 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1172 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1174 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1184 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1187 if (pll->lock)
1188 spin_unlock_irqrestore(pll->lock, flags);
1224 struct tegra_clk_pll *pll = to_clk_pll(hw);
1231 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1232 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1243 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1256 struct tegra_clk_pll *pll = to_clk_pll(hw);
1258 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1307 struct tegra_clk_pll *pll = to_clk_pll(hw);
1314 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1321 if (cfg->p > pll->params->max_p)
1331 struct tegra_clk_pll *pll = to_clk_pll(hw);
1340 if (pll->lock)
1341 spin_lock_irqsave(pll->lock, flags);
1343 _get_pll_mnp(pll, &old_cfg);
1344 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1350 if (pll->lock)
1351 spin_unlock_irqrestore(pll->lock, flags);
1359 struct tegra_clk_pll *pll = to_clk_pll(hw);
1372 if (pll->params->set_gain)
1373 pll->params->set_gain(&cfg);
1381 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1385 val = pll_readl_misc(pll);
1387 pll_writel_misc(val, pll);
1391 pll_writel_misc(val, pll);
1396 struct tegra_clk_pll *pll = to_clk_pll(hw);
1404 if (pll->lock)
1405 spin_lock_irqsave(pll->lock, flags);
1410 val = pll_readl_misc(pll);
1412 pll_writel_misc(val, pll);
1415 _pllcx_strobe(pll);
1417 ret = clk_pll_wait_for_lock(pll);
1419 if (pll->lock)
1420 spin_unlock_irqrestore(pll->lock, flags);
1427 struct tegra_clk_pll *pll = to_clk_pll(hw);
1432 val = pll_readl_misc(pll);
1434 pll_writel_misc(val, pll);
1440 struct tegra_clk_pll *pll = to_clk_pll(hw);
1443 if (pll->lock)
1444 spin_lock_irqsave(pll->lock, flags);
1448 if (pll->lock)
1449 spin_unlock_irqrestore(pll->lock, flags);
1452 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1477 val = pll_readl_misc(pll);
1481 pll_writel_misc(val, pll);
1490 struct tegra_clk_pll *pll = to_clk_pll(hw);
1494 if (pll->lock)
1495 spin_lock_irqsave(pll->lock, flags);
1501 _get_pll_mnp(pll, &old_cfg);
1515 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1519 _update_pll_mnp(pll, &cfg);
1525 if (pll->lock)
1526 spin_unlock_irqrestore(pll->lock, flags);
1531 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1538 m = _pll_fixed_mdiv(pll->params, parent_rate);
1556 struct tegra_clk_pll *pll = to_clk_pll(hw);
1560 if (pll->lock)
1561 spin_lock_irqsave(pll->lock, flags);
1563 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1564 _get_pll_mnp(pll, &old_cfg);
1572 _update_pll_mnp(pll, &cfg);
1576 ret = clk_pll_wait_for_lock(pll);
1580 if (pll->lock)
1581 spin_unlock_irqrestore(pll->lock, flags);
1590 struct tegra_clk_pll *pll = to_clk_pll(hw);
1593 _get_pll_mnp(pll, &cfg);
1604 struct tegra_clk_pll *pll = to_clk_pll(hw);
1606 return _pllre_calc_rate(pll, NULL, rate, *prate);
1611 struct tegra_clk_pll *pll = to_clk_pll(hw);
1620 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1623 if (pll->lock)
1624 spin_lock_irqsave(pll->lock, flags);
1626 val = pll_readl_base(pll);
1628 pll_writel_base(val, pll);
1630 val = pll_readl(pll->params->aux_reg, pll);
1633 pll_writel(val, pll->params->aux_reg, pll);
1636 val = pll_readl_misc(pll);
1642 pll_writel_misc(val, pll);
1645 val = pll_readl(PLLE_SS_CTRL, pll);
1647 pll_writel(val, PLLE_SS_CTRL, pll);
1649 val = pll_readl_base(pll);
1650 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1651 divm_mask_shifted(pll));
1653 val |= sel.m << divm_shift(pll);
1654 val |= sel.n << divn_shift(pll);
1656 pll_writel_base(val, pll);
1660 ret = clk_pll_wait_for_lock(pll);
1665 val = pll_readl(PLLE_SS_CTRL, pll);
1669 pll_writel(val, PLLE_SS_CTRL, pll);
1671 pll_writel(val, PLLE_SS_CTRL, pll);
1674 pll_writel(val, PLLE_SS_CTRL, pll);
1678 val = pll_readl_misc(pll);
1680 pll_writel_misc(val, pll);
1682 val = pll_readl(pll->params->aux_reg, pll);
1685 pll_writel(val, pll->params->aux_reg, pll);
1688 pll_writel(val, pll->params->aux_reg, pll);
1690 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1695 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1698 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1701 val = pll_readl(SATA_PLL_CFG0, pll);
1705 pll_writel(val, SATA_PLL_CFG0, pll);
1709 val = pll_readl(SATA_PLL_CFG0, pll);
1711 pll_writel(val, SATA_PLL_CFG0, pll);
1714 if (pll->lock)
1715 spin_unlock_irqrestore(pll->lock, flags);
1722 struct tegra_clk_pll *pll = to_clk_pll(hw);
1726 if (pll->lock)
1727 spin_lock_irqsave(pll->lock, flags);
1731 val = pll_readl_misc(pll);
1733 pll_writel_misc(val, pll);
1736 if (pll->lock)
1737 spin_unlock_irqrestore(pll->lock, flags);
1742 struct tegra_clk_pll *pll = to_clk_pll(hw);
1757 if (pll->lock)
1758 spin_lock_irqsave(pll->lock, flags);
1763 ret = clk_pll_wait_for_lock(pll);
1781 value = pll_readl_base(pll);
1783 pll_writel_base(value, pll);
1785 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1795 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1797 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1808 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1811 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1815 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1817 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1820 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1828 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1831 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1836 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1838 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1841 if (pll->lock)
1842 spin_unlock_irqrestore(pll->lock, flags);
1847 static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
1852 val = pll_readl_base(pll);
1853 val_aux = pll_readl(pll->params->aux_reg, pll);
1863 pll_writel(val_aux, pll->params->aux_reg, pll);
1864 fence_udelay(1, pll->clk_base);
1873 struct tegra_clk_pll *pll;
1875 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1876 if (!pll)
1879 pll->clk_base = clk_base;
1880 pll->pmc = pmc;
1882 pll->params = pll_params;
1883 pll->lock = lock;
1888 return pll;
1891 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1904 if (!pll->params->calc_rate) {
1905 if (pll->params->flags & TEGRA_PLLM)
1906 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1908 pll->params->calc_rate = _calc_rate;
1911 if (pll->params->set_defaults)
1912 pll->params->set_defaults(pll);
1915 pll->hw.init = &init;
1917 return tegra_clk_dev_register(&pll->hw);
1925 struct tegra_clk_pll *pll;
1930 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1931 if (IS_ERR(pll))
1932 return ERR_CAST(pll);
1934 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1937 kfree(pll);
1956 struct tegra_clk_pll *pll;
1964 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1965 if (IS_ERR(pll))
1966 return ERR_CAST(pll);
1968 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1971 kfree(pll);
1980 struct tegra_clk_pll *pll;
1985 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1986 if (IS_ERR(pll))
1987 return ERR_CAST(pll);
1989 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1992 kfree(pll);
2048 struct tegra_clk_pll *pll;
2072 * If the pll has a set_defaults callback, it will take care of
2094 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2095 if (IS_ERR(pll))
2096 return ERR_CAST(pll);
2098 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2101 kfree(pll);
2113 struct tegra_clk_pll *pll;
2122 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2123 if (IS_ERR(pll))
2124 return ERR_CAST(pll);
2128 val = pll_readl_base(pll);
2136 val = m << divm_shift(pll);
2137 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2138 pll_writel_base(val, pll);
2143 val = pll_readl_misc(pll);
2145 pll_writel_misc(val, pll);
2147 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2150 kfree(pll);
2161 struct tegra_clk_pll *pll;
2185 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2186 if (IS_ERR(pll))
2187 return ERR_CAST(pll);
2189 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2192 kfree(pll);
2205 struct tegra_clk_pll *pll;
2224 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2225 if (IS_ERR(pll))
2226 return ERR_CAST(pll);
2253 pll_writel_base(0, pll);
2254 _update_pll_mnp(pll, &cfg);
2256 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2257 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2258 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2259 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2261 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2263 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2266 kfree(pll);
2277 struct tegra_clk_pll *pll;
2280 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2281 if (IS_ERR(pll))
2282 return ERR_CAST(pll);
2284 _clk_plle_tegra_init_parent(pll);
2286 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2289 kfree(pll);
2300 struct tegra_clk_pll *pll;
2305 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2306 if (IS_ERR(pll))
2307 return ERR_CAST(pll);
2309 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2312 kfree(pll);
2334 struct tegra_clk_pll *pll;
2351 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2352 if (IS_ERR(pll))
2353 return ERR_CAST(pll);
2355 val = pll_readl_base(pll);
2357 pll_writel_base(val, pll);
2371 kfree(pll);
2377 _update_pll_mnp(pll, &cfg);
2379 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2380 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2381 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2382 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2384 val = pll_readl_base(pll);
2389 kfree(pll);
2398 pll_writel_base(val, pll);
2400 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2404 kfree(pll);
2417 struct tegra_clk_pll *pll;
2426 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2427 if (IS_ERR(pll))
2428 return ERR_CAST(pll);
2430 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2433 kfree(pll);
2440 struct tegra_clk_pll *pll = to_clk_pll(hw);
2443 val = pll_readl_base(pll);
2450 struct tegra_clk_pll *pll = to_clk_pll(hw);
2462 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2465 if (pll->lock)
2466 spin_lock_irqsave(pll->lock, flags);
2468 val = pll_readl(pll->params->aux_reg, pll);
2472 val = pll_readl_base(pll);
2474 pll_writel_base(val, pll);
2476 val = pll_readl_misc(pll);
2482 pll_writel_misc(val, pll);
2485 val = pll_readl(PLLE_SS_CTRL, pll);
2487 pll_writel(val, PLLE_SS_CTRL, pll);
2489 val = pll_readl_base(pll);
2490 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2491 divm_mask_shifted(pll));
2493 val |= sel.m << divm_shift(pll);
2494 val |= sel.n << divn_shift(pll);
2496 pll_writel_base(val, pll);
2499 val = pll_readl_base(pll);
2501 pll_writel_base(val, pll);
2503 ret = clk_pll_wait_for_lock(pll);
2508 val = pll_readl(PLLE_SS_CTRL, pll);
2512 pll_writel(val, PLLE_SS_CTRL, pll);
2514 pll_writel(val, PLLE_SS_CTRL, pll);
2517 pll_writel(val, PLLE_SS_CTRL, pll);
2521 if (pll->lock)
2522 spin_unlock_irqrestore(pll->lock, flags);
2529 struct tegra_clk_pll *pll = to_clk_pll(hw);
2533 if (pll->lock)
2534 spin_lock_irqsave(pll->lock, flags);
2537 val = pll_readl(pll->params->aux_reg, pll);
2541 val = pll_readl_base(pll);
2543 pll_writel_base(val, pll);
2545 val = pll_readl(pll->params->aux_reg, pll);
2547 pll_writel(val, pll->params->aux_reg, pll);
2549 val = pll_readl_misc(pll);
2551 pll_writel_misc(val, pll);
2555 if (pll->lock)
2556 spin_unlock_irqrestore(pll->lock, flags);
2561 struct tegra_clk_pll *pll = to_clk_pll(hw);
2563 _clk_plle_tegra_init_parent(pll);
2580 struct tegra_clk_pll *pll;
2583 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2584 if (IS_ERR(pll))
2585 return ERR_CAST(pll);
2587 _clk_plle_tegra_init_parent(pll);
2589 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2592 kfree(pll);
2605 struct tegra_clk_pll *pll;
2627 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2628 if (IS_ERR(pll))
2629 return ERR_CAST(pll);
2631 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2634 kfree(pll);
2645 struct tegra_clk_pll *pll;
2675 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2676 if (IS_ERR(pll))
2677 return ERR_CAST(pll);
2679 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2683 kfree(pll);
2694 struct tegra_clk_pll *pll;
2718 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2719 if (IS_ERR(pll))
2720 return ERR_CAST(pll);
2722 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2725 kfree(pll);