Lines Matching defs:params
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
245 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
246 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
247 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
248 mask(p->params->div_nmp->divp_width))
249 #define sdm_din_mask(p) p->params->sdm_din_mask
250 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
252 #define divm_shift(p) (p)->params->div_nmp->divm_shift
253 #define divn_shift(p) (p)->params->div_nmp->divn_shift
254 #define divp_shift(p) (p)->params->div_nmp->divp_shift
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
287 val |= BIT(pll->params->lock_enable_bit_idx);
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
298 udelay(pll->params->lock_delay);
303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
304 lock_addr += pll->params->misc_reg;
306 lock_addr += pll->params->base_reg;
308 lock_mask = pll->params->lock_mask;
310 for (i = 0; i < pll->params->lock_delay; i++) {
348 if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
361 if (pll->params->iddq_reg) {
362 val = pll_readl(pll->params->iddq_reg, pll);
363 val &= ~BIT(pll->params->iddq_bit_idx);
364 pll_writel(val, pll->params->iddq_reg, pll);
368 if (pll->params->reset_reg) {
369 val = pll_readl(pll->params->reset_reg, pll);
370 val &= ~BIT(pll->params->reset_bit_idx);
371 pll_writel(val, pll->params->reset_reg, pll);
377 if (pll->params->flags & TEGRA_PLL_BYPASS)
382 if (pll->params->flags & TEGRA_PLLM) {
395 if (pll->params->flags & TEGRA_PLL_BYPASS)
400 if (pll->params->flags & TEGRA_PLLM) {
406 if (pll->params->reset_reg) {
407 val = pll_readl(pll->params->reset_reg, pll);
408 val |= BIT(pll->params->reset_bit_idx);
409 pll_writel(val, pll->params->reset_reg, pll);
412 if (pll->params->iddq_reg) {
413 val = pll_readl(pll->params->iddq_reg, pll);
414 val |= BIT(pll->params->iddq_bit_idx);
415 pll_writel(val, pll->params->iddq_reg, pll);
422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
425 val |= pll->params->ssc_ctrl_en_mask;
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
432 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
435 val &= ~pll->params->ssc_ctrl_en_mask;
436 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
483 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
504 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
534 if (pll->params->pdiv_tohw) {
600 cfg->output_rate > pll->params->vco_max) {
607 if (pll->params->pdiv_tohw) {
634 if (!pll->params->sdm_din_reg)
647 val &= ~pll->params->sdm_ctrl_en_mask;
650 val |= pll->params->sdm_ctrl_en_mask;
659 struct tegra_clk_pll_params *params = pll->params;
660 struct div_nmp *div_nmp = params->div_nmp;
662 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
665 val = pll_override_readl(params->pmc_divp_reg, pll);
668 pll_override_writel(val, params->pmc_divp_reg, pll);
670 val = pll_override_readl(params->pmc_divnm_reg, pll);
675 pll_override_writel(val, params->pmc_divnm_reg, pll);
696 struct tegra_clk_pll_params *params = pll->params;
697 struct div_nmp *div_nmp = params->div_nmp;
701 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
704 val = pll_override_readl(params->pmc_divp_reg, pll);
707 val = pll_override_readl(params->pmc_divnm_reg, pll);
717 if (pll->params->sdm_din_reg) {
738 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
742 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
744 if (rate >= (pll->params->vco_max >> 1))
760 if (state && pll->params->pre_rate_change) {
761 ret = pll->params->pre_rate_change();
768 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
770 ret = pll->params->dyn_ramp(pll, cfg);
780 if (!pll->params->defaults_set && pll->params->set_defaults)
781 pll->params->set_defaults(pll);
785 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
795 if (state && pll->params->post_rate_change)
796 pll->params->post_rate_change();
809 if (pll->params->flags & TEGRA_PLL_FIXED) {
810 if (rate != pll->params->fixed_rate) {
813 pll->params->fixed_rate, rate);
820 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
830 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
849 if (pll->params->flags & TEGRA_PLL_FIXED) {
851 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
853 return pll->params->fixed_rate;
857 pll->params->calc_rate(hw, &cfg, rate, *prate))
874 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
877 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
878 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
881 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
887 return pll->params->fixed_rate;
892 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
903 if (pll->params->set_gain)
904 pll->params->set_gain(&cfg);
968 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
984 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
1024 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1025 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1026 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1044 if (pll->params->set_defaults)
1045 pll->params->set_defaults(pll);
1121 const struct utmi_clk_param *params = NULL;
1146 params = &utmi_parameters[i];
1151 if (!params) {
1165 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1167 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1177 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1179 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1231 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1232 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1243 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1258 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1314 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1321 if (cfg->p > pll->params->max_p)
1344 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1372 if (pll->params->set_gain)
1373 pll->params->set_gain(&cfg);
1538 m = _pll_fixed_mdiv(pll->params, parent_rate);
1620 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1630 val = pll_readl(pll->params->aux_reg, pll);
1633 pll_writel(val, pll->params->aux_reg, pll);
1682 val = pll_readl(pll->params->aux_reg, pll);
1685 pll_writel(val, pll->params->aux_reg, pll);
1688 pll_writel(val, pll->params->aux_reg, pll);
1743 const struct utmi_clk_param *params = NULL;
1769 params = &utmi_parameters[i];
1774 if (!params) {
1788 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1790 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1800 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1802 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1853 val_aux = pll_readl(pll->params->aux_reg, pll);
1863 pll_writel(val_aux, pll->params->aux_reg, pll);
1882 pll->params = pll_params;
1904 if (!pll->params->calc_rate) {
1905 if (pll->params->flags & TEGRA_PLLM)
1906 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1908 pll->params->calc_rate = _calc_rate;
1911 if (pll->params->set_defaults)
1912 pll->params->set_defaults(pll);
2462 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2468 val = pll_readl(pll->params->aux_reg, pll);
2537 val = pll_readl(pll->params->aux_reg, pll);
2545 val = pll_readl(pll->params->aux_reg, pll);
2547 pll_writel(val, pll->params->aux_reg, pll);