Lines Matching defs:clk_base
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
302 lock_addr = pll->clk_base;
1002 val = readl(pll->clk_base + PLLE_SS_CTRL);
1005 writel(val, pll->clk_base + PLLE_SS_CTRL);
1162 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1172 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1174 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1184 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1268 void __iomem *clk_base,
1298 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1785 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1795 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1797 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1808 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1811 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1815 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1817 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1820 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1828 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1831 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1836 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1838 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1864 fence_udelay(1, pll->clk_base);
1869 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1879 pll->clk_base = clk_base;
1921 void __iomem *clk_base, void __iomem *pmc,
1930 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1952 void __iomem *clk_base, void __iomem *pmc,
1964 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1977 void __iomem *clk_base, unsigned long flags,
1985 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2043 void __iomem *clk_base, void __iomem *pmc,
2078 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2082 val = readl_relaxed(clk_base + pll_params->base_reg);
2083 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2090 clk_base + pll_params->iddq_reg);
2094 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2107 void __iomem *clk_base, void __iomem *pmc,
2122 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2130 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2156 void __iomem *clk_base, void __iomem *pmc,
2185 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2198 void __iomem *clk_base, void __iomem *pmc,
2224 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2273 void __iomem *clk_base, unsigned long flags,
2280 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2296 void __iomem *clk_base, unsigned long flags,
2305 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2330 void __iomem *clk_base, unsigned long flags,
2351 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2385 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2394 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2412 const char *parent_name, void __iomem *clk_base,
2426 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2576 void __iomem *clk_base, unsigned long flags,
2583 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2598 const char *parent_name, void __iomem *clk_base,
2627 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2640 const char *parent_name, void __iomem *clk_base,
2660 val = readl_relaxed(clk_base + pll_params->base_reg);
2675 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2689 void __iomem *clk_base, void __iomem *pmc,
2718 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);