Lines Matching refs:td
171 * Integrated I2C controller registers - relative to td->i2c_controller_base
331 static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs)
333 return __raw_readl(td->base + offs);
336 static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs)
339 __raw_writel(val, td->base + offs);
342 static inline void dfll_wmb(struct tegra_dfll *td)
344 dfll_readl(td, DFLL_CTRL);
349 static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs)
351 return __raw_readl(td->i2c_base + offs);
354 static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs)
356 __raw_writel(val, td->i2c_base + offs);
359 static inline void dfll_i2c_wmb(struct tegra_dfll *td)
361 dfll_i2c_readl(td, DFLL_I2C_CFG);
366 * @td: DFLL instance
371 static bool dfll_is_running(struct tegra_dfll *td)
373 return td->mode >= DFLL_OPEN_LOOP;
391 struct tegra_dfll *td = dev_get_drvdata(dev);
394 ret = clk_enable(td->ref_clk);
400 ret = clk_enable(td->soc_clk);
403 clk_disable(td->ref_clk);
407 ret = clk_enable(td->i2c_clk);
410 clk_disable(td->soc_clk);
411 clk_disable(td->ref_clk);
428 struct tegra_dfll *td = dev_get_drvdata(dev);
430 clk_disable(td->ref_clk);
431 clk_disable(td->soc_clk);
432 clk_disable(td->i2c_clk);
444 * @td: DFLL instance
450 static void dfll_tune_low(struct tegra_dfll *td)
452 td->tune_range = DFLL_TUNE_LOW;
454 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0);
455 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1);
456 dfll_wmb(td);
458 if (td->soc->set_clock_trimmers_low)
459 td->soc->set_clock_trimmers_low();
486 * @td: DFLL instance
492 static void dfll_set_mode(struct tegra_dfll *td,
495 td->mode = mode;
496 dfll_writel(td, mode - 1, DFLL_CTRL);
497 dfll_wmb(td);
504 static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min)
510 min_uv = td->lut_uv[out_min];
512 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
534 * @td: DFLL instance
540 static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable)
544 val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG);
551 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG);
552 dfll_i2c_wmb(td);
564 * @td: DFLL instance
571 static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable)
577 ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state);
579 dev_err(td->dev, "setting enable state failed\n");
582 val = dfll_readl(td, DFLL_OUTPUT_CFG);
584 div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate);
587 dfll_writel(td, val, DFLL_OUTPUT_CFG);
588 dfll_wmb(td);
591 dfll_writel(td, val, DFLL_OUTPUT_CFG);
592 dfll_wmb(td);
594 ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state);
596 dev_warn(td->dev, "setting disable state failed\n");
598 val = dfll_readl(td, DFLL_OUTPUT_CFG);
600 dfll_writel(td, val, DFLL_OUTPUT_CFG);
601 dfll_wmb(td);
609 * @td: DFLL instance
615 static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val)
617 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
620 dfll_writel(td, val, DFLL_OUTPUT_FORCE);
621 dfll_wmb(td);
623 return dfll_readl(td, DFLL_OUTPUT_FORCE);
628 * @td: DFLL instance
633 static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable)
635 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
642 dfll_writel(td, val, DFLL_OUTPUT_FORCE);
643 dfll_wmb(td);
648 * @td: DFLL instance
653 static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel)
660 val = dfll_set_force_output_value(td, out_sel);
661 if ((td->mode < DFLL_CLOSED_LOOP) &&
663 dfll_set_force_output_enabled(td, true);
671 * @td: struct tegra_dfll *
676 static void dfll_load_i2c_lut(struct tegra_dfll *td)
682 if (i < td->lut_min)
683 lut_index = td->lut_min;
684 else if (i > td->lut_max)
685 lut_index = td->lut_max;
689 val = regulator_list_hardware_vsel(td->vdd_reg,
690 td->lut[lut_index]);
691 __raw_writel(val, td->lut_base + i * 4);
694 dfll_i2c_wmb(td);
699 * @td: DFLL instance
707 static void dfll_init_i2c_if(struct tegra_dfll *td)
711 if (td->i2c_slave_addr > 0x7f) {
712 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT;
715 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT;
719 dfll_i2c_writel(td, val, DFLL_I2C_CFG);
721 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR);
723 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8);
729 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR);
730 dfll_i2c_wmb(td);
735 * @td: DFLL instance
741 static void dfll_init_out_if(struct tegra_dfll *td)
745 td->lut_min = td->lut_bottom;
746 td->lut_max = td->lut_size - 1;
747 td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0);
750 dfll_writel(td, 0, DFLL_OUTPUT_CFG);
751 dfll_wmb(td);
753 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) |
754 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) |
755 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT);
756 dfll_writel(td, val, DFLL_OUTPUT_CFG);
757 dfll_wmb(td);
759 dfll_writel(td, 0, DFLL_OUTPUT_FORCE);
760 dfll_i2c_writel(td, 0, DFLL_INTR_EN);
761 dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK,
764 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) {
765 u32 vinit = td->reg_init_uV;
766 int vstep = td->soc->alignment.step_uv;
767 unsigned long vmin = td->lut_uv[0];
774 dfll_force_output(td, vsel);
777 dfll_load_i2c_lut(td);
778 dfll_init_i2c_if(td);
788 * @td: DFLL instance
796 static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)
801 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
805 align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv;
808 for (i = td->lut_bottom; i < td->lut_size; i++) {
809 if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step)
818 * @td: DFLL instance
827 static int dfll_calculate_rate_request(struct tegra_dfll *td,
840 if (rate < td->dvco_rate_min) {
844 td->dvco_rate_min / 1000);
846 dev_err(td->dev, "%s: Rate %lu is too low\n",
851 rate = td->dvco_rate_min;
855 val = DVCO_RATE_TO_MULT(rate, td->ref_rate);
857 dev_err(td->dev, "%s: Rate %lu is above dfll range\n",
862 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate);
865 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate);
874 * @td: DFLL instance
880 static void dfll_set_frequency_request(struct tegra_dfll *td,
885 int coef = 128; /* FIXME: td->cg_scale? */;
887 force_val = (req->lut_index - td->lut_safe) * coef / td->cg;
896 dfll_writel(td, val, DFLL_FREQ_REQ);
897 dfll_wmb(td);
902 * @td: DFLL instance
912 static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate)
917 if (td->mode == DFLL_UNINITIALIZED) {
918 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n",
919 __func__, mode_name[td->mode]);
923 ret = dfll_calculate_rate_request(td, &req, rate);
927 td->last_unrounded_rate = rate;
928 td->last_req = req;
930 if (td->mode == DFLL_CLOSED_LOOP)
931 dfll_set_frequency_request(td, &td->last_req);
942 * @td: DFLL instance
947 static int dfll_disable(struct tegra_dfll *td)
949 if (td->mode != DFLL_OPEN_LOOP) {
950 dev_err(td->dev, "cannot disable DFLL in %s mode\n",
951 mode_name[td->mode]);
955 dfll_set_mode(td, DFLL_DISABLED);
956 pm_runtime_put_sync(td->dev);
963 * @td: DFLL instance
968 static int dfll_enable(struct tegra_dfll *td)
970 if (td->mode != DFLL_DISABLED) {
971 dev_err(td->dev, "cannot enable DFLL in %s mode\n",
972 mode_name[td->mode]);
976 pm_runtime_get_sync(td->dev);
977 dfll_set_mode(td, DFLL_OPEN_LOOP);
984 * @td: DFLL instance
993 static void dfll_set_open_loop_config(struct tegra_dfll *td)
998 if (td->tune_range != DFLL_TUNE_LOW)
999 dfll_tune_low(td);
1001 val = dfll_readl(td, DFLL_FREQ_REQ);
1004 dfll_writel(td, val, DFLL_FREQ_REQ);
1005 dfll_wmb(td);
1010 * @td: DFLL instance
1016 static int dfll_lock(struct tegra_dfll *td)
1018 struct dfll_rate_req *req = &td->last_req;
1020 switch (td->mode) {
1026 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n",
1031 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1032 dfll_pwm_set_output_enabled(td, true);
1034 dfll_i2c_set_output_enabled(td, true);
1036 dfll_set_mode(td, DFLL_CLOSED_LOOP);
1037 dfll_set_frequency_request(td, req);
1038 dfll_set_force_output_enabled(td, false);
1042 BUG_ON(td->mode > DFLL_CLOSED_LOOP);
1043 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n",
1044 __func__, mode_name[td->mode]);
1051 * @td: DFLL instance
1056 static int dfll_unlock(struct tegra_dfll *td)
1058 switch (td->mode) {
1060 dfll_set_open_loop_config(td);
1061 dfll_set_mode(td, DFLL_OPEN_LOOP);
1062 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1063 dfll_pwm_set_output_enabled(td, false);
1065 dfll_i2c_set_output_enabled(td, false);
1072 BUG_ON(td->mode > DFLL_CLOSED_LOOP);
1073 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n",
1074 __func__, mode_name[td->mode]);
1090 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1092 return dfll_is_running(td);
1097 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1100 ret = dfll_enable(td);
1104 ret = dfll_lock(td);
1106 dfll_disable(td);
1113 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1116 ret = dfll_unlock(td);
1118 dfll_disable(td);
1124 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1126 return td->last_unrounded_rate;
1133 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1137 ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
1153 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1155 return dfll_request_rate(td, rate);
1174 * @td: DFLL instance
1180 static int dfll_register_clk(struct tegra_dfll *td)
1184 dfll_clk_init_data.name = td->output_clock_name;
1185 td->dfll_clk_hw.init = &dfll_clk_init_data;
1187 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw);
1188 if (IS_ERR(td->dfll_clk)) {
1189 dev_err(td->dev, "DFLL clock registration error\n");
1193 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get,
1194 td->dfll_clk);
1196 dev_err(td->dev, "of_clk_add_provider() failed\n");
1198 clk_unregister(td->dfll_clk);
1207 * @td: DFLL instance
1212 static void dfll_unregister_clk(struct tegra_dfll *td)
1214 of_clk_del_provider(td->dev->of_node);
1215 clk_unregister(td->dfll_clk);
1216 td->dfll_clk = NULL;
1244 * @td: DFLL instance
1255 static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
1260 if (!dfll_is_running(td))
1263 v = dfll_readl(td, DFLL_MONITOR_DATA);
1265 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
1267 s = dfll_readl(td, DFLL_FREQ_REQ);
1276 struct tegra_dfll *td = data;
1278 *val = dfll_is_running(td);
1284 struct tegra_dfll *td = data;
1286 return val ? dfll_enable(td) : dfll_disable(td);
1293 struct tegra_dfll *td = data;
1295 *val = (td->mode == DFLL_CLOSED_LOOP);
1301 struct tegra_dfll *td = data;
1303 return val ? dfll_lock(td) : dfll_unlock(td);
1309 struct tegra_dfll *td = data;
1311 *val = dfll_read_monitor_rate(td);
1318 struct tegra_dfll *td = data;
1320 return dfll_request_rate(td, val);
1327 struct tegra_dfll *td = s->private;
1332 val = dfll_i2c_readl(td, offs);
1334 val = dfll_readl(td, offs);
1341 dfll_i2c_readl(td, offs));
1344 dfll_i2c_readl(td, offs));
1346 if (td->pmu_if == TEGRA_DFLL_PMU_I2C) {
1350 __raw_readl(td->i2c_controller_base + offs));
1355 __raw_readl(td->lut_base + offs));
1363 static void dfll_debug_init(struct tegra_dfll *td)
1367 if (!td || (td->mode == DFLL_UNINITIALIZED))
1371 td->debugfs_dir = root;
1373 debugfs_create_file_unsafe("enable", 0644, root, td,
1375 debugfs_create_file_unsafe("lock", 0444, root, td, &lock_fops);
1376 debugfs_create_file_unsafe("rate", 0444, root, td, &rate_fops);
1377 debugfs_create_file("registers", 0444, root, td, &attr_registers_fops);
1381 static inline void dfll_debug_init(struct tegra_dfll *td) { }
1390 * @td: DFLL instance
1396 static void dfll_set_default_params(struct tegra_dfll *td)
1400 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32);
1402 dfll_writel(td, val, DFLL_CONFIG);
1404 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) |
1405 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) |
1406 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) |
1407 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) |
1408 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0);
1409 dfll_writel(td, val, DFLL_PARAMS);
1411 dfll_tune_low(td);
1412 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL);
1413 dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL);
1418 * @td: DFLL instance
1424 static int dfll_init_clks(struct tegra_dfll *td)
1426 td->ref_clk = devm_clk_get(td->dev, "ref");
1427 if (IS_ERR(td->ref_clk)) {
1428 dev_err(td->dev, "missing ref clock\n");
1429 return PTR_ERR(td->ref_clk);
1432 td->soc_clk = devm_clk_get(td->dev, "soc");
1433 if (IS_ERR(td->soc_clk)) {
1434 dev_err(td->dev, "missing soc clock\n");
1435 return PTR_ERR(td->soc_clk);
1438 td->i2c_clk = devm_clk_get(td->dev, "i2c");
1439 if (IS_ERR(td->i2c_clk)) {
1440 dev_err(td->dev, "missing i2c clock\n");
1441 return PTR_ERR(td->i2c_clk);
1443 td->i2c_clk_rate = clk_get_rate(td->i2c_clk);
1450 * @td: DFLL instance
1457 static int dfll_init(struct tegra_dfll *td)
1461 td->ref_rate = clk_get_rate(td->ref_clk);
1462 if (td->ref_rate != REF_CLOCK_RATE) {
1463 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu",
1464 td->ref_rate, REF_CLOCK_RATE);
1468 reset_control_deassert(td->dfll_rst);
1469 reset_control_deassert(td->dvco_rst);
1471 ret = clk_prepare(td->ref_clk);
1473 dev_err(td->dev, "failed to prepare ref_clk\n");
1477 ret = clk_prepare(td->soc_clk);
1479 dev_err(td->dev, "failed to prepare soc_clk\n");
1483 ret = clk_prepare(td->i2c_clk);
1485 dev_err(td->dev, "failed to prepare i2c_clk\n");
1489 td->last_unrounded_rate = 0;
1491 pm_runtime_enable(td->dev);
1492 pm_runtime_get_sync(td->dev);
1494 dfll_set_mode(td, DFLL_DISABLED);
1495 dfll_set_default_params(td);
1497 if (td->soc->init_clock_trimmers)
1498 td->soc->init_clock_trimmers();
1500 dfll_set_open_loop_config(td);
1502 dfll_init_out_if(td);
1504 pm_runtime_put_sync(td->dev);
1509 clk_unprepare(td->soc_clk);
1511 clk_unprepare(td->ref_clk);
1513 reset_control_assert(td->dvco_rst);
1514 reset_control_assert(td->dfll_rst);
1528 struct tegra_dfll *td = dev_get_drvdata(dev);
1530 if (dfll_is_running(td)) {
1531 dev_err(td->dev, "DFLL still enabled while suspending\n");
1535 reset_control_assert(td->dvco_rst);
1536 reset_control_assert(td->dfll_rst);
1553 struct tegra_dfll *td = dev_get_drvdata(dev);
1555 reset_control_deassert(td->dfll_rst);
1556 reset_control_deassert(td->dvco_rst);
1558 pm_runtime_get_sync(td->dev);
1560 dfll_set_mode(td, DFLL_DISABLED);
1561 dfll_set_default_params(td);
1563 if (td->soc->init_clock_trimmers)
1564 td->soc->init_clock_trimmers();
1566 dfll_set_open_loop_config(td);
1568 dfll_init_out_if(td);
1570 pm_runtime_put_sync(td->dev);
1584 static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)
1588 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
1591 align_step = uV / td->soc->alignment.step_uv;
1592 n_voltages = regulator_count_voltages(td->vdd_reg);
1594 reg_uV = regulator_list_voltage(td->vdd_reg, i);
1598 reg_volt_id = reg_uV / td->soc->alignment.step_uv;
1604 dev_err(td->dev, "no voltage map entry for %d uV\n", uV);
1612 static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)
1616 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
1619 align_step = uV / td->soc->alignment.step_uv;
1620 n_voltages = regulator_count_voltages(td->vdd_reg);
1622 reg_uV = regulator_list_voltage(td->vdd_reg, i);
1626 reg_volt_id = reg_uV / td->soc->alignment.step_uv;
1632 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV);
1638 * @td: DFLL instance
1645 static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)
1650 int v_min = td->soc->cvb->min_millivolts * 1000;
1653 reg_volt = td->lut_uv[i];
1660 td->lut[i] = i;
1666 td->lut_size = i;
1668 (lut_bottom + 1 >= td->lut_size)) {
1669 dev_err(td->dev, "no voltage above DFLL minimum %d mV\n",
1670 td->soc->cvb->min_millivolts);
1673 td->lut_bottom = lut_bottom;
1676 rate = get_dvco_rate_below(td, td->lut_bottom);
1678 dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n",
1679 td->soc->cvb->min_millivolts);
1682 td->dvco_rate_min = rate;
1689 * @td: DFLL instance
1695 * the soc-specific platform driver (td->soc->opp_dev) and the PMIC
1698 * On success, fills in td->lut and returns 0, or -err on failure.
1700 static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max)
1706 v = td->soc->cvb->min_millivolts * 1000;
1707 lut = find_vdd_map_entry_exact(td, v);
1710 td->lut[0] = lut;
1711 td->lut_bottom = 0;
1716 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
1721 if (v_opp <= td->soc->cvb->min_millivolts * 1000)
1722 td->dvco_rate_min = dev_pm_opp_get_freq(opp);
1731 selector = find_vdd_map_entry_min(td, v);
1734 if (selector != td->lut[j - 1])
1735 td->lut[j++] = selector;
1739 selector = find_vdd_map_entry_exact(td, v);
1742 if (selector != td->lut[j - 1])
1743 td->lut[j++] = selector;
1748 td->lut_size = j;
1750 if (!td->dvco_rate_min)
1751 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",
1752 td->soc->cvb->min_millivolts);
1755 for (j = 0; j < td->lut_size; j++)
1756 td->lut_uv[j] =
1757 regulator_list_voltage(td->vdd_reg,
1758 td->lut[j]);
1765 static int dfll_build_lut(struct tegra_dfll *td)
1771 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
1773 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");
1779 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1780 return dfll_build_pwm_lut(td, v_max);
1782 return dfll_build_i2c_lut(td, v_max);
1787 * @td: DFLL instance
1795 static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest)
1797 int err = of_property_read_u32(td->dev->of_node, param, dest);
1800 dev_err(td->dev, "failed to read DT parameter %s: %d\n",
1810 * @td: DFLL instance
1816 static int dfll_fetch_i2c_params(struct tegra_dfll *td)
1824 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate))
1827 regmap = regulator_get_regmap(td->vdd_reg);
1831 td->i2c_slave_addr = i2c_client->addr;
1833 ret = regulator_get_hardware_vsel_register(td->vdd_reg,
1837 dev_err(td->dev,
1841 td->i2c_reg = vsel_reg;
1846 static int dfll_fetch_pwm_params(struct tegra_dfll *td)
1851 if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) {
1852 dev_err(td->dev,
1857 td->lut_uv[i] = td->soc->alignment.offset_uv +
1858 i * td->soc->alignment.step_uv;
1860 ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts",
1861 &td->reg_init_uV);
1863 dev_err(td->dev, "couldn't get initialized voltage\n");
1867 ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
1869 dev_err(td->dev, "couldn't get PWM period\n");
1872 td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);
1874 td->pwm_pin = devm_pinctrl_get(td->dev);
1875 if (IS_ERR(td->pwm_pin)) {
1876 dev_err(td->dev, "DT: missing pinctrl device\n");
1877 return PTR_ERR(td->pwm_pin);
1880 td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin,
1882 if (IS_ERR(td->pwm_enable_state)) {
1883 dev_err(td->dev, "DT: missing pwm enabled state\n");
1884 return PTR_ERR(td->pwm_enable_state);
1887 td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin,
1889 if (IS_ERR(td->pwm_disable_state)) {
1890 dev_err(td->dev, "DT: missing pwm disabled state\n");
1891 return PTR_ERR(td->pwm_disable_state);
1899 * @td: DFLL instance
1904 static int dfll_fetch_common_params(struct tegra_dfll *td)
1908 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl);
1909 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate);
1910 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode);
1911 ok &= read_dt_param(td, "nvidia,cf", &td->cf);
1912 ok &= read_dt_param(td, "nvidia,ci", &td->ci);
1913 ok &= read_dt_param(td, "nvidia,cg", &td->cg);
1914 td->cg_scale = of_property_read_bool(td->dev->of_node,
1917 if (of_property_read_string(td->dev->of_node, "clock-output-names",
1918 &td->output_clock_name)) {
1919 dev_err(td->dev, "missing clock-output-names property\n");
1943 struct tegra_dfll *td;
1951 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL);
1952 if (!td)
1954 td->dev = &pdev->dev;
1955 platform_set_drvdata(pdev, td);
1957 td->soc = soc;
1959 td->dfll_rst = devm_reset_control_get_optional(td->dev, "dfll");
1960 if (IS_ERR(td->dfll_rst)) {
1961 dev_err(td->dev, "couldn't get dfll reset\n");
1962 return PTR_ERR(td->dfll_rst);
1965 td->dvco_rst = devm_reset_control_get(td->dev, "dvco");
1966 if (IS_ERR(td->dvco_rst)) {
1967 dev_err(td->dev, "couldn't get dvco reset\n");
1968 return PTR_ERR(td->dvco_rst);
1971 ret = dfll_fetch_common_params(td);
1973 dev_err(td->dev, "couldn't parse device tree parameters\n");
1977 if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) {
1978 td->pmu_if = TEGRA_DFLL_PMU_PWM;
1979 ret = dfll_fetch_pwm_params(td);
1981 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu");
1982 if (IS_ERR(td->vdd_reg)) {
1983 dev_err(td->dev, "couldn't get vdd_cpu regulator\n");
1984 return PTR_ERR(td->vdd_reg);
1986 td->pmu_if = TEGRA_DFLL_PMU_I2C;
1987 ret = dfll_fetch_i2c_params(td);
1992 ret = dfll_build_lut(td);
1994 dev_err(td->dev, "couldn't build LUT\n");
2000 dev_err(td->dev, "no control register resource\n");
2004 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem));
2005 if (!td->base) {
2006 dev_err(td->dev, "couldn't ioremap DFLL control registers\n");
2012 dev_err(td->dev, "no i2c_base resource\n");
2016 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
2017 if (!td->i2c_base) {
2018 dev_err(td->dev, "couldn't ioremap i2c_base resource\n");
2024 dev_err(td->dev, "no i2c_controller_base resource\n");
2028 td->i2c_controller_base = devm_ioremap(td->dev, mem->start,
2030 if (!td->i2c_controller_base) {
2031 dev_err(td->dev,
2038 dev_err(td->dev, "no lut_base resource\n");
2042 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
2043 if (!td->lut_base) {
2044 dev_err(td->dev,
2049 ret = dfll_init_clks(td);
2056 ret = dfll_init(td);
2060 ret = dfll_register_clk(td);
2066 dfll_debug_init(td);
2082 struct tegra_dfll *td = platform_get_drvdata(pdev);
2088 if (td->mode != DFLL_DISABLED) {
2094 debugfs_remove_recursive(td->debugfs_dir);
2096 dfll_unregister_clk(td);
2099 clk_unprepare(td->ref_clk);
2100 clk_unprepare(td->soc_clk);
2101 clk_unprepare(td->i2c_clk);
2103 reset_control_assert(td->dvco_rst);
2104 reset_control_assert(td->dfll_rst);
2106 return td->soc;