Lines Matching refs:rate
13 static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,
25 if (tmp_rate > rate)
28 if ((rate - tmp_rate) < (rate - best_rate)) {
44 unsigned long rate,
58 * unsigned long in rate * m * p below
61 maxdiv = min(ULONG_MAX / rate, maxdiv);
70 if (rate * div == parent_rate_saved) {
73 * rate can be divided from parent clock without
74 * needing to change parent rate, so return the
78 return rate;
81 parent_rate = clk_hw_round_rate(hw, rate * div);
84 if (now <= rate && now > best_rate) {
88 if (now == rate)
89 return rate;
100 unsigned long rate,
108 rate *= cmp->fixed_post_div;
114 rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
116 rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
121 rate /= cmp->fixed_post_div;
123 return rate;
151 unsigned long rate;
170 rate = (parent_rate >> p) / m;
172 rate /= cmp->fixed_post_div;
174 return rate;
186 static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
202 /* Adjust target rate according to post-dividers */
204 rate = rate * cmp->fixed_post_div;
206 ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
260 * mode is active, the clock output rate is halved. This new class
271 unsigned long rate = ccu_mp_recalc_rate(hw, parent_rate);
276 return rate / 2;
277 return rate;
287 /* adjust the requested clock rate */
289 req->rate *= 2;
296 /* re-adjust the requested clock rate back */
298 req->rate /= 2;
306 static int ccu_mp_mmc_set_rate(struct clk_hw *hw, unsigned long rate,
313 rate *= 2;
315 return ccu_mp_set_rate(hw, rate, parent_rate);