Lines Matching defs:reg
19 return !(readl(common->base + common->reg) & cf->enable);
27 u32 reg;
33 reg = readl(common->base + common->reg);
34 writel(reg & ~cf->enable, common->base + common->reg);
43 u32 reg;
49 reg = readl(common->base + common->reg);
50 writel(reg | cf->enable, common->base + common->reg);
69 u32 reg;
79 reg = readl(common->base + common->reg);
81 pr_debug("%s: clock reg is 0x%x (select is 0x%x)\n",
82 clk_hw_get_name(&common->hw), reg, cf->select);
84 return (reg & cf->select) ? cf->rates[1] : cf->rates[0];
93 u32 reg, sel;
106 reg = readl(common->base + common->reg);
107 reg &= ~cf->select;
108 writel(reg | sel, common->base + common->reg);