Lines Matching refs:rate
14 * Fref: OSC source clock rate
304 unsigned long rate;
312 * rate = parent * (fbdiv + frac/2^24) / prediv / 2^postdiv1
316 rate = parent_rate * val.frac / (1UL << 24);
318 rate = 0;
322 rate += parent_rate * val.fbdiv;
323 rate /= val.prediv << val.postdiv1;
325 return rate;
335 /* if the parent rate doesn't match our expectations the presets won't work */
337 req->rate = jh7110_pll_recalc_rate(hw, req->best_parent_rate);
341 /* find highest rate lower or equal to the requested rate */
345 if (req->rate < val->freq)
351 req->rate = selected->freq;
355 static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
364 /* if the parent rate doesn't match our expectations the presets won't work */
369 if (val->freq == rate)