Lines Matching refs:reg
44 unsigned long fdiv, reg, rdiv, qdiv;
47 /* read VCO1 reg for numerator and denominator */
48 reg = readl(socfpgaclk->hw.reg + 0x8);
49 fdiv = (reg & SOCFPGA_N5X_PLLDIV_FDIV_MASK) >> SOCFPGA_N5X_PLLDIV_FDIV_SHIFT;
50 rdiv = (reg & SOCFPGA_N5X_PLLDIV_RDIV_MASK);
51 qdiv = (reg & SOCFPGA_N5X_PLLDIV_QDIV_MASK) >> SOCFPGA_N5X_PLLDIV_QDIV_SHIFT;
65 unsigned long arefdiv, reg, mdiv;
68 /* read VCO1 reg for numerator and denominator */
69 reg = readl(socfpgaclk->hw.reg);
70 arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
75 reg = readl(socfpgaclk->hw.reg + 0x24);
76 mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK;
88 unsigned long reg;
91 /* read VCO1 reg for numerator and denominator */
92 reg = readl(socfpgaclk->hw.reg);
93 refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
99 reg = readl(socfpgaclk->hw.reg + 0x4);
100 mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
112 div = ((readl(socfpgaclk->hw.reg) &
125 pll_src = readl(socfpgaclk->hw.reg);
135 pll_src = readl(socfpgaclk->hw.reg);
143 u32 reg;
146 reg = readl(socfpgaclk->hw.reg);
147 reg |= SOCFPGA_PLL_RESET_MASK;
148 writel(reg, socfpgaclk->hw.reg);
156 u32 reg;
159 reg = readl(socfpgaclk->hw.reg + 0x4);
160 reg |= SOCFPGA_PLL_RESET_MASK;
161 writel(reg, socfpgaclk->hw.reg + 0x4);
191 void __iomem *reg)
203 pll_clk->hw.reg = reg + clks->offset;
231 void __iomem *reg)
243 pll_clk->hw.reg = reg + clks->offset;
270 void __iomem *reg)
282 pll_clk->hw.reg = reg + clks->offset;