clk-pll.c - OpenGrok cross reference for /kernel/linux/linux-6.6/drivers/clk/samsung/clk-pll.c

Lines Matching refs:pll_con0
327 	u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
331 	pll_con0 = readl_relaxed(pll->con_reg);
333 	mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
334 	pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
335 	sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
346 	const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)
350 	old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
351 	old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
362 	u32 pll_con0, pll_con1;
372 	pll_con0 = readl_relaxed(pll->con_reg);
375 	if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
377 		pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
378 		pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
379 		writel_relaxed(pll_con0, pll->con_reg);
388 	pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
391 	pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
394 	writel_relaxed(pll_con0, pll->con_reg);
400 	if (pll_con0 & BIT(pll->enable_offs))
637 static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
642 	old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
643 	old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
753 	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
756 	pll_con0 = readl_relaxed(pll->con_reg);
758 	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
760 	pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
761 	sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
774 static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
779 	old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
780 	old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
922 	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
925 	pll_con0 = readl_relaxed(pll->con_reg);
927 	mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
928 	pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
929 	sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
1102 	u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
1105 	pll_con0 = readl_relaxed(pll->con_reg);
1106 	mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK;
1107 	pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK;
1108 	sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK;
1193 	u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
1197 	pll_con0 = readl_relaxed(pll->con_reg);
1199 	mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
1200 	pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
1201 	sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
1215 	u32 pll_con0, pll_con2;
1225 	pll_con0 = readl_relaxed(pll->con_reg);
1229 	pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
1232 	pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
1233 	pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
1234 	pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
1235 	pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
1236 	pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
1245 	writel_relaxed(pll_con0, pll->con_reg);