Lines Matching defs:con0
655 u32 con0, con1;
665 con0 = readl_relaxed(pll->con_reg);
668 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
670 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
671 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
672 writel_relaxed(con0, pll->con_reg);
678 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
681 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
704 writel_relaxed(con0, pll->con_reg);
792 u32 con0, con1, lock;
802 con0 = readl_relaxed(pll->con_reg);
805 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
807 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
808 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
809 writel_relaxed(con0, pll->con_reg);
822 con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
826 con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
830 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
833 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
848 writel_relaxed(con0, pll->con_reg);
1125 u32 con0, con1;
1135 con0 = readl_relaxed(pll->con_reg);
1142 con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) |
1145 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) |
1148 con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT);
1149 writel_relaxed(con0, pll->con_reg);