Lines Matching refs:MUX_SEL_DISP1
2501 #define MUX_SEL_DISP1 0x0204
2535 MUX_SEL_DISP1,
2563 { MUX_SEL_DISP1, 0 },
2652 /* MUX_SEL_DISP1 */
2654 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2656 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2658 MUX_SEL_DISP1, 20, 1),
2660 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2662 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2664 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2666 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2668 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),