Lines Matching refs:clk_table
130 struct clk_hw **clk_table;
152 clk_table = clk_data->hws;
183 clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
194 clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
199 clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
203 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
207 clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
211 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
215 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
219 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
223 clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
230 clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
235 clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
241 if (IS_ERR(clk_table[i])) {
243 ret = PTR_ERR(clk_table[i]);