Lines Matching refs:list
408 struct rockchip_pll_clock *list,
414 for (idx = 0; idx < nr_pll; idx++, list++) {
415 clk = rockchip_clk_register_pll(ctx, list->type, list->name,
416 list->parent_names, list->num_parents,
417 list->con_offset, grf_lock_offset,
418 list->lock_shift, list->mode_offset,
419 list->mode_shift, list->rate_table,
420 list->flags, list->pll_flags);
423 list->name);
427 rockchip_clk_add_lookup(ctx, clk, list->id);
433 struct rockchip_clk_branch *list,
440 for (idx = 0; idx < nr_clk; idx++, list++) {
441 flags = list->flags;
444 switch (list->branch_type) {
446 if (list->mux_table)
447 clk = clk_register_mux_table(NULL, list->name,
448 list->parent_names, list->num_parents,
450 ctx->reg_base + list->muxdiv_offset,
451 list->mux_shift, list->mux_width,
452 list->mux_flags, list->mux_table,
455 clk = clk_register_mux(NULL, list->name,
456 list->parent_names, list->num_parents,
458 ctx->reg_base + list->muxdiv_offset,
459 list->mux_shift, list->mux_width,
460 list->mux_flags, &ctx->lock);
463 clk = rockchip_clk_register_muxgrf(list->name,
464 list->parent_names, list->num_parents,
465 flags, ctx->grf, list->muxdiv_offset,
466 list->mux_shift, list->mux_width,
467 list->mux_flags);
470 if (list->div_table)
472 list->name, list->parent_names[0],
474 ctx->reg_base + list->muxdiv_offset,
475 list->div_shift, list->div_width,
476 list->div_flags, list->div_table,
479 clk = clk_register_divider(NULL, list->name,
480 list->parent_names[0], flags,
481 ctx->reg_base + list->muxdiv_offset,
482 list->div_shift, list->div_width,
483 list->div_flags, &ctx->lock);
486 clk = rockchip_clk_register_frac_branch(ctx, list->name,
487 list->parent_names, list->num_parents,
488 ctx->reg_base, list->muxdiv_offset,
489 list->div_flags,
490 list->gate_offset, list->gate_shift,
491 list->gate_flags, flags, list->child,
495 clk = rockchip_clk_register_halfdiv(list->name,
496 list->parent_names, list->num_parents,
497 ctx->reg_base, list->muxdiv_offset,
498 list->mux_shift, list->mux_width,
499 list->mux_flags, list->div_shift,
500 list->div_width, list->div_flags,
501 list->gate_offset, list->gate_shift,
502 list->gate_flags, flags, &ctx->lock);
507 clk = clk_register_gate(NULL, list->name,
508 list->parent_names[0], flags,
509 ctx->reg_base + list->gate_offset,
510 list->gate_shift, list->gate_flags, &ctx->lock);
513 clk = rockchip_clk_register_branch(list->name,
514 list->parent_names, list->num_parents,
515 ctx->reg_base, list->muxdiv_offset,
516 list->mux_shift,
517 list->mux_width, list->mux_flags,
518 list->mux_table, list->div_offset,
519 list->div_shift, list->div_width,
520 list->div_flags, list->div_table,
521 list->gate_offset, list->gate_shift,
522 list->gate_flags, flags, &ctx->lock);
526 list->name,
527 list->parent_names, list->num_parents,
528 ctx->reg_base + list->muxdiv_offset,
529 list->div_shift
534 list->name, list->parent_names,
535 list->num_parents,
536 ctx->reg_base + list->muxdiv_offset,
537 list->div_shift, list->div_flags, &ctx->lock);
541 list->name, list->parent_names,
542 list->num_parents, ctx->reg_base,
543 list->div_shift, list->div_width,
544 list->gate_offset, list->gate_shift,
545 list->gate_flags, flags, &ctx->lock);
549 list->name, list->flags,
550 list->parent_names, list->num_parents,
551 list->muxdiv_offset, list->mux_shift,
552 list->mux_width, list->div_shift,
553 list->div_width, list->div_flags,
561 __func__, list->branch_type);
567 __func__, list->name, PTR_ERR(clk));
571 rockchip_clk_add_lookup(ctx, clk, list->id);