Lines Matching defs:gpll_cpll_p
452 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
705 COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL,
708 COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL,
711 COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL,
714 COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
717 COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL,
720 COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL,
726 COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL,
729 COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0,
732 COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL,
735 COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL,
750 COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
774 COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
792 COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0,
795 COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0,
798 COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0,
998 COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL,
1076 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
1081 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
1086 COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
1238 COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0,
1247 COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0,
1256 COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0,
1265 COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0,
1274 COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0,
1283 COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0,
1292 COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0,
1301 COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0,
1310 COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0,
1459 COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,
1467 COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0,
1484 COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0,
1487 COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0,
1491 COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL,
1494 COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL,
1584 COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0,
1587 COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0,
1590 COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0,
1636 COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0,
1642 COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0,
1651 COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0,
1657 COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0,
1672 COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0,
1702 COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0,
1810 COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0,
1819 COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0,
1908 COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0,
1914 COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0,
1941 COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
1985 COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0,
1992 COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0,