Lines Matching refs:rate
49 unsigned long rate = clk_hw_get_rate(hw);
55 if (!rate)
65 36 * (rate / 10000);
78 unsigned long rate = clk_hw_get_rate(hw);
87 * the clock rate from its parent, namely the output clock
96 if (!rate) {
97 pr_err("%s: invalid clk rate\n", __func__);
130 (rate / 1000) * 36 *
167 * process. However if the clock rate is changed, the phase is stale
174 * (2) the new coming rate is higher than the older one since mmc driver