clk-cpu.c - OpenGrok cross reference for /kernel/linux/linux-6.6/drivers/clk/rockchip/clk-cpu.c

Lines Matching refs:cpuclk
68 			    struct rockchip_cpuclk *cpuclk, unsigned long rate)
71 							cpuclk->rate_table;
74 	for (i = 0; i < cpuclk->rate_count; i++) {
85 	struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
86 	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
87 	u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
98 static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
112 		writel(clksel->val, cpuclk->reg_base + clksel->reg);
116 static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk,
130 		writel(clksel->val, cpuclk->reg_base + clksel->reg);
134 static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk,
148 		writel(clksel->val, cpuclk->reg_base + clksel->reg);
152 static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
155 	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
162 	rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
164 		pr_err("%s: Invalid rate : %lu for cpuclk\n",
169 	alt_prate = clk_get_rate(cpuclk->alt_parent);
171 	spin_lock_irqsave(cpuclk->lock, flags);
201 			       cpuclk->reg_base + reg_data->core_reg[i]);
205 	rockchip_cpuclk_set_pre_muxs(cpuclk, rate);
212 		       cpuclk->reg_base + reg_data->mux_core_reg);
217 		       cpuclk->reg_base + reg_data->core_reg[0]);
219 	spin_unlock_irqrestore(cpuclk->lock, flags);
223 static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
226 	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
231 	rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
233 		pr_err("%s: Invalid rate : %lu for cpuclk\n",
238 	spin_lock_irqsave(cpuclk->lock, flags);
241 		rockchip_cpuclk_set_dividers(cpuclk, rate);
254 		       cpuclk->reg_base + reg_data->mux_core_reg);
259 		       cpuclk->reg_base + reg_data->core_reg[0]);
261 	rockchip_cpuclk_set_post_muxs(cpuclk, rate);
267 		       cpuclk->reg_base + reg_data->core_reg[i]);
271 		rockchip_cpuclk_set_dividers(cpuclk, rate);
273 	spin_unlock_irqrestore(cpuclk->lock, flags);
279  * of cpuclk is to be changed. This notifier handles the setting up all
287 	struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);
293 		ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata);
295 		ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata);
306 	struct rockchip_cpuclk *cpuclk;
316 	cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
317 	if (!cpuclk)
333 	cpuclk->reg_base = reg_base;
334 	cpuclk->lock = lock;
335 	cpuclk->reg_data = reg_data;
336 	cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
337 	cpuclk->hw.init = &init;
339 	cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
340 	if (!cpuclk->alt_parent) {
347 	ret = clk_prepare_enable(cpuclk->alt_parent);
363 	ret = clk_notifier_register(clk, &cpuclk->clk_nb);
371 		cpuclk->rate_count = nrates;
372 		cpuclk->rate_table = kmemdup(rates,
375 		if (!cpuclk->rate_table) {
381 	cclk = clk_register(NULL, &cpuclk->hw);
383 		pr_err("%s: could not register cpuclk %s\n", __func__,	name);
391 	kfree(cpuclk->rate_table);
393 	clk_notifier_unregister(clk, &cpuclk->clk_nb);
395 	clk_disable_unprepare(cpuclk->alt_parent);
397 	kfree(cpuclk);