Lines Matching refs:_id
126 #define DEF_TYPE(_name, _id, _type...) \
127 { .name = _name, .id = _id, .type = _type }
128 #define DEF_BASE(_name, _id, _type, _parent...) \
129 DEF_TYPE(_name, _id, _type, .parent = _parent)
130 #define DEF_SAMPLL(_name, _id, _parent, _conf) \
131 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
132 #define DEF_INPUT(_name, _id) \
133 DEF_TYPE(_name, _id, CLK_TYPE_IN)
134 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \
135 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
136 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
137 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
140 #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
141 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
144 #define DEF_MUX(_name, _id, _conf, _parent_names) \
145 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
149 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
150 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
154 #define DEF_SD_MUX(_name, _id, _conf, _parent_names) \
155 DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
158 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \
159 DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)
160 #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \
161 DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \
164 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \
165 DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag)
186 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \
189 .id = MOD_CLK_BASE + (_id), \
196 #define DEF_MOD(_name, _id, _parent, _off, _bit) \
197 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
199 #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \
200 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
215 #define DEF_RST_MON(_id, _off, _bit, _monbit) \
216 [_id] = { \
221 #define DEF_RST(_id, _off, _bit) \
222 DEF_RST_MON(_id, _off, _bit, -1)