Lines Matching refs:value
201 * Setting a value of '0' to the SEL_SDHI0_SET or SEL_SDHI1_SET clock
204 * the index to value mapping is done by adding 1 to the index.
363 * Based on the dot clock, the DSI divider clock sets the divider value,
602 /* Output clock setting, SSCG modulation value setting 3 */
900 u32 value;
913 value = (bitmask << 16) | bitmask;
915 value = bitmask << 16;
916 writel(value, priv->base + CLK_ON_R(reg));
926 error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value,
927 value & bitmask, 0, 10);
980 u32 value;
991 value = readl(priv->base + CLK_MON_R(clock->off));
993 value = readl(priv->base + clock->off);
995 return value & bitmask;
1116 u32 value = mask << 16;
1120 writel(value, priv->base + CLK_RST_R(reg));
1133 return readl_poll_timeout_atomic(priv->base + reg, value,
1134 value & mask, 10, 200);
1145 u32 value = (mask << 16) | mask;
1150 writel(value, priv->base + CLK_RST_R(reg));
1163 return readl_poll_timeout_atomic(priv->base + reg, value,
1164 !(value & mask), 10, 200);