Lines Matching refs:init
20 #include <linux/init.h>
257 struct clk_init_data init;
268 init.name = GET_SHIFT(core->conf) ? "sd1" : "sd0";
269 init.ops = &rzg2l_cpg_sd_clk_mux_ops;
270 init.flags = 0;
271 init.num_parents = core->num_parents;
272 init.parent_names = core->parent_names;
275 clk_hw->init = &init;
394 struct clk_init_data init;
409 init.name = core->name;
410 init.ops = &rzg2l_cpg_dsi_div_ops;
411 init.flags = CLK_SET_RATE_PARENT;
412 init.parent_names = &parent_name;
413 init.num_parents = 1;
416 clk_hw->init = &init;
488 struct clk_init_data init;
499 init.name = core->name;
500 init.ops = &rzg2l_cpg_pll5_4_clk_mux_ops;
501 init.flags = CLK_SET_RATE_PARENT;
502 init.num_parents = core->num_parents;
503 init.parent_names = core->parent_names;
506 clk_hw->init = &init;
640 struct clk_init_data init;
654 init.name = core->name;
656 init.ops = &rzg2l_cpg_sipll5_ops;
657 init.flags = 0;
658 init.parent_names = &parent_name;
659 init.num_parents = 1;
661 sipll5->hw.init = &init;
669 clk_hw->init = &init;
724 struct clk_init_data init;
737 init.name = core->name;
738 init.ops = &rzg2l_cpg_pll_ops;
739 init.flags = 0;
740 init.parent_names = &parent_name;
741 init.num_parents = 1;
743 pll_clk->hw.init = &init;
1034 struct clk_init_data init;
1061 init.name = mod->name;
1062 init.ops = &rzg2l_mod_clock_ops;
1063 init.flags = CLK_SET_RATE_PARENT;
1068 init.flags |= CLK_IS_CRITICAL;
1073 init.parent_names = &parent_name;
1074 init.num_parents = 1;
1079 clock->hw.init = &init;