Lines Matching defs:clk_hw
62 struct clk_hw hw;
133 struct clk_hw *clk_hw;
142 clk_hw = clk_hw_register_divider_table(dev, core->name,
151 clk_hw = clk_hw_register_divider(dev, core->name,
158 if (IS_ERR(clk_hw))
159 return ERR_CAST(clk_hw);
161 return clk_hw->clk;
169 const struct clk_hw *clk_hw;
171 clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
178 if (IS_ERR(clk_hw))
179 return ERR_CAST(clk_hw);
181 return clk_hw->clk;
184 static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
233 static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
258 struct clk_hw *clk_hw;
274 clk_hw = &clk_hw_data->hw;
275 clk_hw->init = &init;
277 ret = devm_clk_hw_register(priv->dev, clk_hw);
281 return clk_hw->clk;
306 struct clk_hw hw;
314 static unsigned long rzg2l_cpg_dsi_div_recalc_rate(struct clk_hw *hw,
326 static unsigned long rzg2l_cpg_get_vclk_parent_rate(struct clk_hw *hw,
342 static int rzg2l_cpg_dsi_div_determine_rate(struct clk_hw *hw,
353 static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw,
395 struct clk_hw *clk_hw;
415 clk_hw = &clk_hw_data->hw;
416 clk_hw->init = &init;
418 ret = devm_clk_hw_register(priv->dev, clk_hw);
422 return clk_hw->clk;
426 struct clk_hw hw;
434 static int rzg2l_cpg_pll5_4_clk_mux_determine_rate(struct clk_hw *hw,
437 struct clk_hw *parent;
448 static int rzg2l_cpg_pll5_4_clk_mux_set_parent(struct clk_hw *hw, u8 index)
469 static u8 rzg2l_cpg_pll5_4_clk_mux_get_parent(struct clk_hw *hw)
489 struct clk_hw *clk_hw;
505 clk_hw = &clk_hw_data->hw;
506 clk_hw->init = &init;
508 ret = devm_clk_hw_register(priv->dev, clk_hw);
512 return clk_hw->clk;
516 struct clk_hw hw;
524 static unsigned long rzg2l_cpg_get_vclk_rate(struct clk_hw *hw,
540 static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
552 static long rzg2l_cpg_sipll5_round_rate(struct clk_hw *hw,
559 static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
643 struct clk_hw *clk_hw;
668 clk_hw = &sipll5->hw;
669 clk_hw->init = &init;
671 ret = devm_clk_hw_register(priv->dev, clk_hw);
679 return clk_hw->clk;
683 struct clk_hw hw;
692 static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
882 struct clk_hw hw;
892 static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
935 static int rzg2l_mod_clock_enable(struct clk_hw *hw)
955 static void rzg2l_mod_clock_disable(struct clk_hw *hw)
975 static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
1008 struct clk_hw *hw;